From 2df2697107d7873232c31a25a6947711b0903edb Mon Sep 17 00:00:00 2001
From: Max Christian Pohle
Date: Mon, 27 Jul 2015 15:12:22 +0200
Subject: latest running version from march 2011, not having been in repo
 before, dcf77 working, mp3 playback and two display types are supported

---
 src/inc/int/dcf77/clock.c      | 157 +++++++++++++++++++++++++++++++++++++
 src/inc/int/dcf77/clock.h      |  98 +++++++++++++++++++++++
 src/inc/pwm/pwm.c              |  13 ++++
 src/inc/pwm/pwm.h              |   3 +
 src/inc/spi/dev/audio_vs1011.c | 173 +++++++++++++++++++++++++++++++++++++++++
 src/inc/spi/dev/audio_vs1011.h |  91 ++++++++++++++++++++++
 src/inc/spi/dev/display_dogm.c |  39 ++++++++++
 src/inc/spi/dev/display_dogm.h |  31 ++++++++
 src/inc/spi/dev/petit          |   1 +
 src/inc/spi/spi.c              |  56 +++++++++++++
 src/inc/spi/spi.h              |  37 +++++++++
 src/inc/stdalg.c               |  29 +++++++
 src/inc/stdalg.h               |   8 ++
 src/inc/stdout.c               | 154 ++++++++++++++++++++++++++++++++++++
 src/inc/stdout.h               |  41 ++++++++++
 src/inc/uart/uart.c            |  47 +++++++++++
 src/inc/uart/uart.h            |  17 ++++
 17 files changed, 995 insertions(+)
 create mode 100755 src/inc/int/dcf77/clock.c
 create mode 100755 src/inc/int/dcf77/clock.h
 create mode 100755 src/inc/pwm/pwm.c
 create mode 100755 src/inc/pwm/pwm.h
 create mode 100755 src/inc/spi/dev/audio_vs1011.c
 create mode 100755 src/inc/spi/dev/audio_vs1011.h
 create mode 100755 src/inc/spi/dev/display_dogm.c
 create mode 100755 src/inc/spi/dev/display_dogm.h
 create mode 160000 src/inc/spi/dev/petit
 create mode 100755 src/inc/spi/spi.c
 create mode 100755 src/inc/spi/spi.h
 create mode 100755 src/inc/stdalg.c
 create mode 100755 src/inc/stdalg.h
 create mode 100755 src/inc/stdout.c
 create mode 100755 src/inc/stdout.h
 create mode 100755 src/inc/uart/uart.c
 create mode 100755 src/inc/uart/uart.h

(limited to 'src/inc')

diff --git a/src/inc/int/dcf77/clock.c b/src/inc/int/dcf77/clock.c
new file mode 100755
index 0000000..75f33fe
--- /dev/null
+++ b/src/inc/int/dcf77/clock.c
@@ -0,0 +1,157 @@
+#include "clock.h"
+
+
+// returns -1 on error
+unsigned char getBits(const DCF start, const char len, const DCF pbit)
+{
+  static const unsigned char mult[]  = {1, 2, 4, 8, 10, 20 ,40 ,80};
+  /// unsigned char p = 1; //parity
+  unsigned char r = 0; // retval
+  unsigned char i;
+  for(i=0; i<len; i++)
+  {
+    r += dcf77[start+i].bit * mult[i];
+    /// if(dcf77[start+i].bit)
+      /// p ^= 1;
+  }
+
+  // 1110011
+  //  001000
+
+  // 8
+  // 72
+
+  /// if((pbit != DCF_FIRST) && (dcf77[pbit].bit != p))
+    /// return -1;
+  /// else
+    return r;
+}
+
+void set_dcf_value()
+{
+  // check for parity
+  /// if
+  /// (
+    /// (dcf77[DCF_FIRST].bit            != 0 ) |
+    /// (dcf77[DCF_START].bit            != 1 ) |
+    /// (getBits(DCF_MIN, 7, DCF_MINP)   == -1) |
+    /// (getBits(DCF_MIN, 7, DCF_START)   > 59) |
+    /// (getBits(DCF_HOUR, 6, DCF_HOURP) == -1)
+  /// ) return;
+
+  // set new time
+  t_current.m = (getBits(DCF_MIN,      7, DCF_START)) - 1;
+  t_current.h = (getBits(DCF_HOUR,     6, DCF_START));
+  t_current.dd = (getBits(DCF_DAY,     6, DCF_START));
+  t_current.wd = (getBits(DCF_WEEKDAY, 3, DCF_START));
+  t_current.mm = (getBits(DCF_MONTH,   5, DCF_START));
+  t_current.yy = (getBits(DCF_YEAR,    8, DCF_START));
+}
+
+//                                                       7372800/a=10000
+//                                                       115200 / a * x = 10000
+//                                                       7372800/8/150
+ISR(TIMER0_COMP_vect) // called 10000 times per second (12000000/8/150)
+{
+  //cli();
+  // F_CPU / PRESCALER / (OCR0 + 1)
+  if(++t_current.us >= 10) // one u-second
+  {
+    t_current.us = 0; // restart
+    // interval length of dcf77 can be greater than 1000 ms... count it!
+    ++interval;
+
+    /*
+    cli();
+    if(t_current.ms <= 500)
+    { OCR1A = 50 + (200 - (t_current.ms / 3)); }
+    else
+    { OCR1A = 50 + (200 - ((1000 - t_current.ms) / 3)); }
+    sei();
+    */
+
+    if(++t_current.ms >= 1000) // one second
+    {
+      t_current.ms = 0; // restart
+      if(++t_current.s > 59) // one minute
+      {
+        t_current.s = 0; // restart
+        if(++t_current.m > 59) // one hour
+        {
+          t_current.m = 0; // restart
+          if(++t_current.h > 23) // one day
+          {
+            t_current.h = 0; // restart
+            t_current.dd++;
+          }
+        }
+      }
+    }
+  }
+  //sei();
+}
+
+ISR(INT0_vect)
+{
+  /// stdout_put_int(interval, uart_putc);
+  /// stdout_put_string("INT0 call\n", uart_putc);
+  cli();
+  if(INT0_CONTROL == INT0_RISING_EDGE)
+  {
+    if(interval > 1000 && interval < 2000)  // 59th second - no rising edge at the beginning
+    {
+      /// if(dcf77_bit == 59) // check if every bit has been transfered
+      set_dcf_value();  // completely received- apply new time data
+
+      // 59th second: synchronize with receiver...
+      dcf77_bit    = 0;
+      TCNT0        = 0;
+      t_current.s  = 0;
+      t_current.ms = 0;
+      t_current.us = 0;
+    }
+    INT0_CONTROL = INT0_FALLING_EDGE;
+  }
+  else // INT0_FALLING_EDGE
+  {
+    dcf77[dcf77_bit++].bit = interval >= 200 ? 1 : 0;
+    lastinterval = interval;
+
+    INT0_CONTROL = INT0_RISING_EDGE;
+  }
+
+  interval = 0; // reset interval to count next interval
+  sei();
+}
+
+
+void timer_init()
+{
+  // 7372800/8
+  DDRD &= ~((1<<PD2) | (1<<PD3)); // make INT0 and INT1 input-pins
+
+  // Prescaler...
+  TCCR0  = (0<<CS02) | (1<<CS01) | (0<<CS00) | (1<<WGM01);
+  // output compare...
+  OCR0   = 149;
+  //OCR0   = 152 - 1;
+  //TCCR0 |= (0<<WGM01) | (1<<WGM01);
+
+  // ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
+  // ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
+  // CSx: set prescaler (010 means 8)
+  /// TCCR1B = (1<<ICNC1) | (1<<ICES1) | (0<<CS12) | (1<<CS11) | (0<<CS10);
+  // OCIE0: Output Compare Match Interrupt Enable
+  // TICIE: Timer/Counter Input Capture Interrupt Enable
+  TIMSK |= (1<<OCIE0);
+
+  // interrupts_init...
+  // General Interrupt Mask Register (enables interrupts)
+  //GIMSK |= (1<<INT0);
+  GICR |= (1<<INT0);
+  // MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
+  //MCUCR |= (0<<ISC01) | (1<<ISC00); // any logical change generates interrupt
+  INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
+  /// loworhigh.bit = 0;
+}
+
diff --git a/src/inc/int/dcf77/clock.h b/src/inc/int/dcf77/clock.h
new file mode 100755
index 0000000..c7f75c7
--- /dev/null
+++ b/src/inc/int/dcf77/clock.h
@@ -0,0 +1,98 @@
+#ifndef CLOCK_H
+#define CLOCK_H
+  /* this dcf77-module relies on a accuarate clock (cristal) for receiving
+   * the dcf-signal. therefor the clock is going to work as expected,
+   * even with no dcf77-signal available.
+   * receivement is automatically turned on, if the avr is connected to the
+   * signal via INT0. if there is no signal the clock will not be set (K.I.S.S.)
+   *
+   */
+  #include <stdint.h>
+  #include <avr/io.h>
+  #include <avr/interrupt.h>
+  #include <limits.h>
+
+  /// #include "../stdout.h"
+  /// #include "../display/display.h"
+  /// #include "../uart/uart.h"
+
+  #define INT0_CONTROL       MCUCR
+  #define INT0_FALLING_EDGE  0x02
+  #define INT0_RISING_EDGE   0x03
+
+
+
+  typedef struct
+  {
+    volatile unsigned char bit : 1;
+  } Bit;
+
+  typedef struct
+  {
+    unsigned char h ;  // hour
+    unsigned char m ;  // minute
+    unsigned char s ;  // second
+    unsigned char dd;  // day
+    unsigned char wd;  // weekday
+    unsigned char mm;  // month
+    unsigned char yy;  // year
+    unsigned char us; // 10th second
+    unsigned int ms;  // milli second
+  } Time;
+
+  typedef enum
+  {
+    DCF_FIRST   = 0,  // start of a new minute (note: always 0)
+    DCF_WEATHER = 14, // proprietary :-(
+    DCF_ANTENNA = 15, // 0: normal, 1: replacement
+    DCF_DST     = 16, // daylight saving time: this hour new time...
+    DCF_MEZ     = 17, // 'summer-time'
+    DCF_MESZ    = 18, // 'winter-time'
+    DCF_DBLSEC  = 19, // one extra second gonna be inserted
+    DCF_START   = 20, // begin of time-info (note: always 1)
+    DCF_MIN     = 21, // 7 bit
+    DCF_MINP    = 28, // parity bit for minutes
+    DCF_HOUR    = 29, // 6 bit
+    DCF_HOURP   = 35, // parity bit for hours
+    DCF_DAY     = 36, // 6 bit
+    DCF_WEEKDAY = 42, // 3 bit
+    DCF_MONTH   = 45, // 5 bit
+    DCF_YEAR    = 50, // 8 bit
+    DCF_DATEP   = 58  // parity bit for date
+  } DCF;
+
+  /*
+  typedef struct
+  {
+    Bit useless[14];
+    Bit antenna;
+    Bit dst;
+    Bit mez;
+    Bit mesz;
+    Bit dblsec;
+    Bit start;               // < always 1 - use for verification
+    unsigned char min   : 7;
+    Bit min_p;               // < minutes parity
+    unsigned char hour  : 6;
+    Bit hour_p;              // < hours parity
+    unsigned char day   : 6; // day of month
+    unsigned char dow   : 3; // day of week (1=monday)
+    unsigned char month : 5; // month of year
+    unsigned char year  : 8; // year
+    Bit date_p;              // parity of date
+  } DCF_Signal;
+  */
+
+
+  volatile Bit dcf77[60];
+  volatile unsigned char dcf77_bit;
+  volatile Time t_current;
+  volatile unsigned int interval;
+  volatile unsigned int lastinterval;
+
+  /// void getBits(volatile unsigned char* target, const DCF start, const char len, const DCF parity);
+  /// void set_dcf_value();
+  void timer_init();
+  /// void interrupts_init();
+
+#endif
diff --git a/src/inc/pwm/pwm.c b/src/inc/pwm/pwm.c
new file mode 100755
index 0000000..fac9347
--- /dev/null
+++ b/src/inc/pwm/pwm.c
@@ -0,0 +1,13 @@
+
+void pwminit()
+{
+  TCCR0 |= (1<<WGM01);
+}
+
+void pwm_setInterval()
+{
+  /// if(t_current.ms <= 500)
+  /// { OCR1A = 50 + (200 - (t_current.ms / 3)); }
+  /// else
+  /// { OCR1A = 50 + (200 - ((1000 - t_current.ms) / 3)); }
+}
diff --git a/src/inc/pwm/pwm.h b/src/inc/pwm/pwm.h
new file mode 100755
index 0000000..8b671bc
--- /dev/null
+++ b/src/inc/pwm/pwm.h
@@ -0,0 +1,3 @@
+#include <avr/io.h>
+
+void pwminit();
diff --git a/src/inc/spi/dev/audio_vs1011.c b/src/inc/spi/dev/audio_vs1011.c
new file mode 100755
index 0000000..ad44654
--- /dev/null
+++ b/src/inc/spi/dev/audio_vs1011.c
@@ -0,0 +1,173 @@
+#include "audio_vs1011.h"
+/// inline void audio_vs1011_setVolume(unsigned char left, unsigned char right)
+/// { audio_vs1011_cmd(SCI_VOL, left, right); }
+
+void audio_vs1011_init()
+{
+  // [initialize pins and ports]
+  DDRC  |= ((1<<PC1) | (1<<PC2) | (1<<PC4)); // XCS/XDCS/RESET
+  DDRC  &= ~(1<<PC3); // DREQ
+  //DDRA  |=  (1<<PA6); // activate O-Port A6 as [XCS]
+  //DDRC  |=  (1<<PC6); // activate O-Port C6 as [XDCS]
+  //DDRD  |=  (1<<PD6); // activate O-Port D6 as [RESET]
+  //DDRD  &= ~(1<<PD5); // activate I-Port D5 as [DREQ]
+
+
+  // pins...
+  /// PORTA |= (1<<PA6);
+  /// PORTC |= (1<<PC6);
+  PORTC |= (1<<PC3);        // enable pullup resistor for [DREQ]
+  audio_vs1011_exit_xcs();  // activate XCS: deactivate vs1011-cmd-line
+  audio_vs1011_exit_xdcs(); // activate XDCS: deactivate vs1011-data-line
+
+  // [reset vs1011]
+  // this ensures, that it finds XCS and XDCS in proper state (see below)
+  /// PORTD &= ~(1<<PD6); // <reset>
+  // Wait for at least 10 ms after startup (required!!)
+  // then make GPIO an output signal and set it to 1...
+  /// _delay_ms(20);
+  PORTC |= (1<<PC4);  // </reset>
+  /// _delay_ms(20);
+
+  // wait until DREQ is set- so chip has rebooted from reset...
+  wait4dreq();
+
+  // [set vs1011 to 'new-mode']
+  // where xdcs is driven low, before you want to send mp3-data or test-bits
+  // where xcs is driven low to send SCI-commands.
+  // and both together may not been activated, why we started with resetting
+  // after having configured those output-ports.
+  audio_vs1011_cmd(SCI_MODE, (SM_SDINEW | SM_TESTS));
+
+  // [set clock-frequency...]
+  // formular:
+  //     32768{if clock doubler}
+  //   + (F_CRYSTAL{crystals frequency in Hz} / 2000{const})
+  //   = 0x9770 for a 12MHz-crystal (with clock-doubler), so send:
+  /// audio_vs1011_cmd(SCI_CLOCKF, 0x98, 0x00);
+  /// stdout_put_uint(uart_putc, ((F_CPU / 2000) | SC_CLK2X));
+  /// stdout_put_string(uart_putc, "\t< clock freq for vs1011\n");
+
+  audio_vs1011_cmd(SCI_CLOCKF, ((F_CPU / 2000) | SC_CLK2X));
+  audio_vs1011_cmd(SCI_AUDATA, 44100);
+
+  /*
+  spi_setspeed(SPICLK_FAST);
+  int q;
+  for(q=0; q<=30000; q++)
+    spi_putc(0x00);
+  spi_setspeed(SPICLK_DEFAULT);
+  // wait for at least 11000 clock cycles...
+  */
+
+  // wait until DREQ is set- so chip has rebooted from reset...
+  wait4dreq();
+
+
+  /// spi_putc(0xFF);
+
+  audio_vs1011_setVolume(1, 1); // left and right both to 100%=0xFF
+  /// _delay_ms(250);
+
+  /// stdout_put_string(uart_putc, "clock frequency set!\n");
+}
+
+
+void audio_vs1011_setVolume(const unsigned char left, const unsigned char right)
+{
+  //uint16_t volume = right + (256 * left);
+  /// stdout_put_uint(uart_putc, volume);
+  /// stdout_put_string(uart_putc, "\t< new volume for vs1011\n");
+  audio_vs1011_cmd(SCI_VOL, ((uint16_t) right) + ((uint16_t) left * 256));
+}
+
+void audio_vs1011_test_volume()
+{
+  audio_vs1011_setVolume(0, 0); // left and right to 0%=0x00 -> standby
+  _delay_ms(250);
+  audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
+  _delay_ms(250);
+}
+
+void audio_vs1011_test_sine()
+{
+  static const unsigned char sinetest[] = {0x53, 0xEF, 0x6E, 0x30, 0x0, 0x0, 0x0, 0x0};
+  static const unsigned char testexit[] = {'E', 'x', 'i', 't', 0x0, 0x0, 0x0, 0x0};
+
+  /// audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
+  /// stdout_put_string(uart_putc, "activating sine-test...\n");
+  audio_vs1011_dat(sinetest, sizeof(sinetest));
+  _delay_ms(250);
+
+  /// stdout_put_string(uart_putc, "deactivating sine-test...\n");
+  audio_vs1011_dat(testexit, sizeof(testexit));
+  _delay_ms(250);
+  /// audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
+}
+
+/*
+void audio_vs1011_test_eeprom()
+{
+  unsigned char block[512];
+  eeprom_read_block((void*) &block, (const void*) 0, 512);
+
+  int i,q;
+  for(i=0; i<512; i+=32)
+  {
+    audio_vs1011_enable();
+    loop_until_bit_is_set(PIND, PD5);
+    for(q=0; q<32; q++)
+      spi_putc(block[i+q]);
+    audio_vs1011_disable();
+ }
+  loop_until_bit_is_set(PIND, PD5);
+ _delay_ms(500);
+}
+*/
+
+void audio_vs1011_dat(const unsigned char* dat, const unsigned char size)
+{
+  audio_vs1011_enable();
+  unsigned char i;
+  for(i=0; i<size; i++)
+    spi_putc(dat[i]);
+  audio_vs1011_disable();
+}
+
+
+/*
+unsigned char audio_vs1011_stream(unsigned char (*readfn)())
+{
+  audio_vs1011_enable();
+  register unsigned char i;
+  for(i=0; i<32; i++)
+    spi_putc(readfn());
+  audio_vs1011_disable();
+  audio_vs1011_waitDREQ();
+  return 32;
+}*/
+
+
+
+
+void audio_vs1011_cmd(const unsigned char cmd, uint16_t dat)
+{
+  loop_until_bit_is_set(PIND, PD5);
+  /// audio_vs1011_enable();
+  //PORTA &= ~(1<<PA6); // <XCS>
+  audio_vs1011_init_xcs();
+  spi_putc(VS_WRITE);
+  spi_putc(cmd);
+  spi_putc((dat >> 8) & 0xFF);
+  spi_putc((dat >> 0) & 0xFF);
+  //PORTA |=  (1<<PA6); // </XCS>
+  audio_vs1011_exit_xcs();
+  spi_putc(0);
+  spi_putc(0);
+  spi_putc(0);
+  spi_putc(0);
+  /// audio_vs1011_disable();
+  /// _delay_ms(1);       // << wait to make sure vs1011 got the message
+  _delay_ms(5);
+  loop_until_bit_is_set(PIND, PD5); // << wait for DREQ to become ready again
+}
diff --git a/src/inc/spi/dev/audio_vs1011.h b/src/inc/spi/dev/audio_vs1011.h
new file mode 100755
index 0000000..ec97550
--- /dev/null
+++ b/src/inc/spi/dev/audio_vs1011.h
@@ -0,0 +1,91 @@
+#ifndef AUDIO_VS1011_H
+#define AUDIO_VS1011_H
+
+  #include <avr/io.h>
+  #include <util/delay.h>
+  #include <inttypes.h>
+  #include <avr/eeprom.h>
+
+  #include "../spi.h"
+  /// #include "../../uart/uart.h"
+  /// #include "../../stdout.h"
+
+
+  #define audio_vs1011_enable()  PORTC &= ~(1<<PC6); // <XDCS>
+  #define audio_vs1011_disable() PORTC |=  (1<<PC6); // </XDCS>
+  #define audio_vs1011_isDREQ()  (PIND & (1<<PD5))
+  #define audio_vs1011_waitDREQ(); loop_until_bit_is_set(PIND, PD5);
+
+
+  // [OPERATIONS]
+  #define VS_WRITE 0x2
+  #define VS_READ  0x3
+
+
+  // [SCI REGISTERS] - page 29
+  #define SCI_MODE        0x0 // Mode control
+  #define SCI_STATUS      0x1 // Status of VS1011e
+  #define SCI_BASS        0x2 // Built-in bass/treble enhancer
+  #define SCI_CLOCKF      0x3 // Clock freq + multiplier
+  #define SCI_DECODE_TIME 0x4 // Decode time in seconds
+  #define SCI_AUDATA      0x5 // Misc. audio data
+  #define SCI_WRAM        0x6 // RAM write/read
+  #define SCI_WRAMADDR    0x7 // Base address for RAM write/read
+  #define SCI_HDAT0       0x8 // Stream header data 0
+  #define SCI_HDAT1       0x9 // Stream header data 1
+  #define SCI_AIADDR      0xA // Start address of application
+  #define SCI_VOL         0xB // Volume control
+  #define SCI_AICTRL0     0xC // Application control register 0
+  #define SCI_AICTRL1     0xD // Application control register 1
+  #define SCI_AICTRL2     0xE // Application control register 2
+  #define SCI_AICTRL3     0xF // Application control register 3
+
+  // [VALUES::SCI_MODE]
+  #define SM_DIFF       0x1    // Differential
+  #define SM_LAYER12    0x2    // Allow MPEG layers I & II
+  #define SM_RESET      0x4    // Soft reset
+  #define SM_OUTOFWAV   0x8    // Jump out of WAV decoding
+  #define SM_SETTOZERO1 0x10   // set to zero
+  #define SM_TESTS      0x20   // Allow SDI tests
+  #define SM_STREAM     0x40   // Stream mode
+  #define SM_SETTOZERO2 0x80   // set to zero
+
+  #define SM_DACT       0x100  // DCLK active edge
+  #define SM_SDIORD     0x200  // SDI bit order
+  #define SM_SDISHARE   0x400  // Share SPI chip select
+  #define SM_SDINEW     0x800  // VS1002 native SPI modes
+  #define SM_SETTOZERO3 0x1000 // set to zero
+
+  // [VALUES::SCI_CLOCKF]
+  #define SC_CLK2X      0x8000 // clock doubler
+
+  #define audio_vs1011_init_xcs()    PORTC &= ~(1<<PC1)  // <XCS>
+  #define audio_vs1011_exit_xcs()    PORTC |=  (1<<PC1); // </XCS>
+
+  #define audio_vs1011_init_xdcs()   PORTC &= ~(1<<PC2)  // <XCS>
+  #define audio_vs1011_exit_xdcs()   PORTC |=  (1<<PC2); // </XCS>
+
+  #define wait4dreq() loop_until_bit_is_set(PINC, PC3);  // <DREQ></DREQ>
+
+
+  /// void audio_vs1011_cmd(const unsigned char sci_cmd, const unsigned char hdata,
+    /// const unsigned char ldata);
+  void audio_vs1011_init();
+  void audio_vs1011_cmd(const unsigned char cmd, uint16_t dat);
+  void audio_vs1011_setVolume(const unsigned char left, const unsigned char right);
+
+  //void audio_vs1011_dat(const unsigned char dat[32]);
+  void audio_vs1011_dat(const unsigned char* dat, const unsigned char size);
+  /// unsigned char audio_vs1011_stream(unsigned char (*readfn)());
+  void audio_vs1011_test_sine();
+  void audio_vs1011_test_volume();
+  /// void audio_vs1011_test_eeprom();
+  /// void audio_vs1011_enable();
+  /// void audio_vs1011_disable();
+  /// char audio_vs1011_isDREQ();
+
+
+  /// void audio_vs1011_test_softreset();
+
+
+#endif
diff --git a/src/inc/spi/dev/display_dogm.c b/src/inc/spi/dev/display_dogm.c
new file mode 100755
index 0000000..a655769
--- /dev/null
+++ b/src/inc/spi/dev/display_dogm.c
@@ -0,0 +1,39 @@
+#include "display_dogm.h"
+
+void display_dogm_init()
+{
+  //DDRA |= (1<<PA7); // activate portA for display
+  //DDRC |= (1<<PC7); // activate portC for display
+  DDRD  |= (1<<PD7) | (1<<PD6);
+  PORTD |= (1<<PD7) | (1<<PD6);
+
+  // Wait time >40mS after VDD stable
+  _delay_ms(50); // 10ms for safty
+
+  display_dogm_exec(CMD_FUNCTION_SET);
+  display_dogm_exec(CMD_FUNCTION_SET);
+  display_dogm_exec(CMD_CONTRAST_SET);
+  display_dogm_exec(CMD_POWER_CONTROL);
+  display_dogm_exec(CMD_FOLLOWER_CONTROL);
+  display_dogm_exec(CMD_DISPLAY_ONOFF);
+  display_dogm_exec(CMD_ENTRY_MODE_SET);
+  display_dogm_exec(CMD_DISPLAY_CLEAR);
+}
+
+void display_dogm_putc(char c)
+{
+  PORTD &= ~(1<<PD7); // chip select: activate display
+  PORTD |=  (1<<PD6); // L=Commandmode, H=Datamode
+  spi_putc(c);
+  _delay_us(40);      // try and error value (you get chinese chars? increase!)
+  PORTD |=  (1<<PD7); // chip select: deactivate display
+}
+
+void display_dogm_exec(char c)
+{
+  PORTD &= ~(1<<PD7); // chip select: activate display
+  PORTD &= ~(1<<PD6); // L=Commandmode, H=Datamode
+  spi_putc(c);
+  _delay_ms(4);       // time the longest command takes on display
+  PORTD |=  (1<<PD7); // chip select: deactivate display
+}
diff --git a/src/inc/spi/dev/display_dogm.h b/src/inc/spi/dev/display_dogm.h
new file mode 100755
index 0000000..d9cf560
--- /dev/null
+++ b/src/inc/spi/dev/display_dogm.h
@@ -0,0 +1,31 @@
+#ifndef DISPLAY_DOGM_H
+#define DISPLAY_DOGM_H
+
+  #include <avr/io.h>
+  #include <util/delay.h>
+  #include "../spi.h"
+
+  #define CONTAST              3
+
+  #define CMD_FUNCTION_SET          32 + 16 + 8 + 0 + 1
+  #define CMD_POWER_CONTROL    64 +  0 + 16 + 0 + 4 + CONTAST
+  #define CMD_FOLLOWER_CONTROL 0x6E
+
+  #define CMD_ENTRY_MODE_SET   4 + 2 + 0
+  #define CMD_DISPLAY_HOME     0 + 2 + 0
+  #define CMD_DISPLAY_CLEAR    0 + 0 + 1
+
+  #define CMD_CONTRAST_SET     0x7F
+  #define CMD_FUNCTION_SET2    0x38
+  #define CMD_DISPLAY_ONOFF    0x0C
+  #define CMD_DISPLAY_POS      0x80
+
+  //#define display_dogm_enable()  PORTD &= ~(1<<PD7); PORTD |=  (1<<PD6); // <XDCS>
+  //#define display_dogm_disable() PORTD |=  (1<<PD7); PORTD &= ~(1<<PD6); // </XDCS>
+
+
+  void display_dogm_init();
+  void display_dogm_putc(char);
+  void display_dogm_exec(char);
+
+#endif
diff --git a/src/inc/spi/dev/petit b/src/inc/spi/dev/petit
new file mode 160000
index 0000000..b110953
--- /dev/null
+++ b/src/inc/spi/dev/petit
@@ -0,0 +1 @@
+Subproject commit b1109539d5d34b62849d67a65ce244fcb1d0f5e5
diff --git a/src/inc/spi/spi.c b/src/inc/spi/spi.c
new file mode 100755
index 0000000..b04fe7e
--- /dev/null
+++ b/src/inc/spi/spi.c
@@ -0,0 +1,56 @@
+#include "spi.h"
+
+void spi_init()
+{
+  // setup SPI-Port
+  DDR_SPI   = (1<<DD_MOSI) | (1<<DD_SS) | (1<<DD_SCK);
+  PORT_SPI |=  (1<<DD_SS);
+
+  // SPI Control Register (SPCR)
+  // SPI Enable=1 | Data Order=LSB | SPI_Master=1 (!make SS stay HIGH!)
+  // SPCR |= (1<<SPE) | (1<<DORD) | (1<<MSTR) | (1<<CPOL) | (1<<CPHA) | (1<<SPR1) | (1<<SPR0);
+  // (1<<DORD) - would be LSB-mode (, but we need MSB-mode!)
+  SPCR  = (1<<SPE) | (1<<MSTR); //  (1<<SPR1) | (1<<SPR0)
+  spi_setspeed(SPICLK_DEFAULT);
+  // setup SPI options
+  /// SPSR &= ~(1<<SPI2X); // do not use SPI speed-doubler
+}
+
+void spi_setspeed(SPICLK speed)
+{
+  if(speed < 4) // nominal clock speeds
+  {
+    SPSR &= ~(1<<SPI2X); // do not use SPI speed-doubler
+    SPCR |= speed;
+  }
+  else // use SPI2X
+  {
+    SPSR |= (1<<SPI2X);  // use SPI speed-doubler
+    SPCR |= (speed - 0x4);
+  }
+  _delay_ms(2);
+}
+
+void spi_putc(unsigned char c)
+{
+  /// uart_putc('>');
+  /// uart_putc(c);
+  /// uart_putc('\n');
+  SPDR = c;
+  loop_until_bit_is_set(SPSR, SPIF);
+  /// stdout_put_string(uart_putc, "- [done]\n");
+}
+
+unsigned char spi_getc()
+{
+  SPDR = 0xFF; // init receive register with value
+  /* Wait for reception complete */
+  while(!(SPSR & (1<<SPIF)));
+  /* Return data register */
+  return SPDR;
+  /// unsigned char c = SPDR;
+  /// uart_putc('<');
+  /// uart_putc(c);
+  /// uart_putc('\n');
+  /// return c;
+}
diff --git a/src/inc/spi/spi.h b/src/inc/spi/spi.h
new file mode 100755
index 0000000..bb92cac
--- /dev/null
+++ b/src/inc/spi/spi.h
@@ -0,0 +1,37 @@
+#ifndef SPI_H
+#define SPI_H
+
+  #include <avr/io.h>
+  #include <util/delay.h>
+  #include "../uart/uart.h"
+  #include "../stdout.h"
+
+  #define SPICLK_DEFAULT  SPICLK_64
+  #define SPICLK_FAST     SPICLK_X2
+
+  #define PORT_SPI        PORTB
+  #define DDR_SPI         DDRB
+  #define DD_SS           DDB4
+  #define DD_MOSI         DDB5
+  #define DD_MISO         DDB6
+  #define DD_SCK          DDB7
+
+  typedef enum
+  {
+    SPICLK_4,   // vv nominal clk-speeds
+    SPICLK_16,
+    SPICLK_64,
+    SPICLK_128,
+    SPICLK_X2,   // vv with SPI2x
+    SPICLK_X32,
+    SPICLK_X64
+  } SPICLK;
+
+
+  void spi_init();
+  void spi_putc(unsigned char c);
+  unsigned char spi_getc();
+  void spi_setspeed(SPICLK speed);
+
+
+#endif
diff --git a/src/inc/stdalg.c b/src/inc/stdalg.c
new file mode 100755
index 0000000..99558a9
--- /dev/null
+++ b/src/inc/stdalg.c
@@ -0,0 +1,29 @@
+#include "stdalg.h"
+
+#ifdef STDALGO_CRC7
+  unsigned char crc7(unsigned char* bytes, unsigned char size)
+  {
+    register unsigned char val = 0; // last cycles value
+    register unsigned char cb;      // current byte.
+
+    unsigned char i;
+    for(i=0; i<=size; i++)
+    {
+      cb = bytes[i];
+
+      int q = (i==size) ? 7 : 8; // counter
+      do
+      {
+        val <<= 1;
+        if(cb & 0x80)         // check MSB of current byte
+          ++val;              // overflow, add 1
+
+        if(val & 0x80)        // check MSB of (last) seed
+          val ^= 0x9;         // polynome
+        cb     <<= 1;
+      } while(--q);
+      val &= 0x7f;            // lower 7 bits
+    }
+    return ((val<<1) + 1);
+  }
+#endif
diff --git a/src/inc/stdalg.h b/src/inc/stdalg.h
new file mode 100755
index 0000000..5f31cc5
--- /dev/null
+++ b/src/inc/stdalg.h
@@ -0,0 +1,8 @@
+#ifndef STDALG_H
+#define STDALG_H
+
+  #ifdef STDALGO_CRC7
+    unsigned char crc7(unsigned char* bytes, unsigned char size);
+  #endif
+
+#endif
diff --git a/src/inc/stdout.c b/src/inc/stdout.c
new file mode 100755
index 0000000..0160e0b
--- /dev/null
+++ b/src/inc/stdout.c
@@ -0,0 +1,154 @@
+#include "stdout.h"
+
+#ifdef STDOUT_put_string
+  void stdout_put_string(void (*putc)(char c), const char* s)
+  {
+    register unsigned char c;
+    while ((c=*s++))
+      putc(c);
+  }
+#endif
+
+#ifdef STDOUT_put_uint
+  void stdout_put_uint(void (*putc)(const char c), int n)
+  {
+    unsigned char i;
+    for(i=0; _devisor_ten[i]>n; i++);
+    int c=0;
+    for(; i<sizeof(_devisor_ten) / sizeof(int); i++)
+    {
+      for(c=0; (n - _devisor_ten[i]) < n; c++)
+        n -= _devisor_ten[i];
+      putc('0' + c);
+    }
+    /// // if processor has can devide this might be better:
+    /// register unsigned int d=1;
+    /// for(; d<n; d*=10);
+    /// for(d /= 10; d>0; n %= d, d /= 10)
+      /// putc('0' + (n / d));
+  }
+#endif
+
+#ifdef STDOUT_reverse_bits
+  char stdout_reverse_bits(unsigned char v)
+  {
+    unsigned char s = sizeof(v) * CHAR_BIT; // bit size; must be power of 2
+    unsigned char mask = ~0;
+    while ((s >>= 1) > 0)
+    {
+      mask ^= (mask << s);
+      v = ((v >> s) & mask) | ((v << s) & ~mask);
+    }
+    return v;
+  }
+#endif
+
+#ifdef STDOUT_put_binary
+  void stdout_put_binary(void (*putc)(const char c), const unsigned char data)
+  {
+    char i;
+    for(i=CHAR_BIT-1; i>=0; i--)
+    {
+      if(data & (1<<i))
+        putc('1');
+      else
+        putc('0');
+    }
+  }
+#endif
+
+#ifdef STDOUT_putf
+void stdout_putf(void (*putc)(const char c), const char* format, ...)
+{
+  va_list vl;
+  va_start(vl, format);
+
+  typedef union
+  {
+    char as_char         : (sizeof(char) * CHAR_BIT);
+    int as_int           : (sizeof(int) * CHAR_BIT);
+    uint32_t as_uint     : (sizeof(int) * CHAR_BIT);
+  } va_data;
+  va_data data;
+
+  do
+  {
+    if(format[0] != '%')
+      putc(format[0]);
+    else
+    {
+      char f = '\0'; // fill-char for fixed width numbers (\0 means OFF)
+      switch((++format)[0])
+      {
+        case '%':
+          putc('%');
+        break;
+        case 'c':
+          putc(va_arg(vl, int));
+        break;
+        case '0':
+          if(f == '\0')
+            f = '0';
+        case '-':
+          if(f == '\0')
+            f = ' ';
+        case ' ':
+        case 'd':
+        {
+          int width = 0;
+          data.as_int = va_arg(vl, unsigned int);
+
+          if(data.as_int < 0)
+          {
+            putc('-');
+            width        = -1;
+            data.as_int *= -1;
+          }
+          else if(format[0] == ' ')
+              putc(' ');
+
+          if(f != '\0')
+          {
+            // translate string with user-requested fixed length...
+            static const int _potences[] = {1, 10, 100, 1000};
+
+            int s     = 0;
+            while((++format)[1] !='d' && format[0] >='0' && format[0] <='9')
+              s++;
+            for(; s>=0; --s)
+              width += _potences[sizeof(_potences) - s] * (format[-s] - '0');
+
+            // count numbers width in decimal-system...
+            for(s=10; s<data.as_int; s*=10, --width);
+
+            // remove trailing numbers and append spacechar if wanted...
+            for(; width>1; width--, putc(f)); // prepend whitespace-character[space]
+          }
+
+          stdout_put_uint(putc, data.as_uint);
+          if(format[0] != 'd')
+            ++format;
+        }
+        break;
+        case 's':
+          #ifdef STDOUT_put_string
+            stdout_put_string(putc, va_arg(vl, char*));
+          #else
+            va_arg(vl, int); // remove next argument
+          #endif
+        break;
+        case 'b':
+          #ifdef STDOUT_put_binary
+            data.as_int = va_arg(vl, int);
+            stdout_put_binary(putc, data.as_uint);
+          #else
+            va_arg(vl, int); // remove next argument
+          #endif
+        break;
+      }
+    }
+  }
+  while((++format)[0] != '\0');
+  return;
+}
+#endif
diff --git a/src/inc/stdout.h b/src/inc/stdout.h
new file mode 100755
index 0000000..da7027f
--- /dev/null
+++ b/src/inc/stdout.h
@@ -0,0 +1,41 @@
+#ifndef STDOUT_H
+#define STDOUT_H
+  #include <inttypes.h>
+  #include <limits.h>
+
+  #ifdef STDOUT_put_string
+    void stdout_put_string(void (*putc)(const char c), const char* s);
+  #endif
+
+  #ifdef STDOUT_put_uint
+    static const unsigned int _devisor_two[] =
+    {
+      /// 2147483648, 1073741824, 536870912, 268435456, 134217728, 67108864,
+      /// 33554432, 16777216, 8388608, 4194304, 2097152, 1048576, 524288, 262144,
+      /// 131072, 65536,
+      32768, 16384, 8192, 4096, 2048, 1024, 512, 256, 128, 64,
+      32, 16, 8, 4, 2, 1
+    };
+    static const unsigned int _devisor_ten[] =
+    {
+      /// 1000000000, 100000000, 10000000, 1000000, 100000,
+      10000, 1000, 100, 10, 1
+    };
+    void stdout_put_uint(void (*putc)(const char c), int n);
+  #endif
+
+  #ifdef STDOUT_put_binary
+    void stdout_put_binary(void (*putc)( const char c), const unsigned char data);
+  #endif
+
+  #ifdef STDOUT_reverse_bits
+    char stdout_reverse_bits(const unsigned char v);
+  #endif
+
+  #ifdef STDOUT_putf
+    #include <stdarg.h>
+    extern void dec_put_char(const char);
+    void stdout_putf(void (*putc)( const char c), const char* format, ...);
+  #endif
+
+#endif
diff --git a/src/inc/uart/uart.c b/src/inc/uart/uart.c
new file mode 100755
index 0000000..b2f1a59
--- /dev/null
+++ b/src/inc/uart/uart.c
@@ -0,0 +1,47 @@
+#include "uart.h"
+
+/// // UART-Receiver...
+/// ISR(USART_RXC_vect)
+/// {
+  /// unsigned char buffer;
+  /// buffer = UDR;
+  /// if(uart_string.size == -1) return;
+  /// if(buffer == '\n')
+  /// {
+    /// uart_string.data[uart_string.size] = '\0';
+    /// uart_string.size = -1;
+  /// }
+  /// else
+  /// {
+    /// uart_string.data[uart_string.size] = buffer;
+    /// if(++uart_string.size > STRING_SIZE)
+    /// { uart_string.size = 0; }
+  /// }
+/// }
+
+void uart_init()
+{
+  /// uart_string.size = 0;
+  /// uart_string.data[0] = '\0';
+
+  // activate UART TX // and RX...
+  UCSRB |= (1<<TXEN); // | (1<<RXEN) | (1<<RXCIE);
+  // Asynchron 8N1 ...
+  UCSRC |= (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0);
+
+  UBRRH = UBRRH_VALUE;
+  UBRRL = UBRRL_VALUE;
+  #if USE_2X
+    UCSRA |= (1 << U2X);
+  #else
+    UCSRA &= ~(1 << U2X);
+  #endif
+}
+
+void uart_putc(char c)
+{
+  UDR = c; /* schreibt das Zeichen x auf die Schnittstelle */
+  loop_until_bit_is_set(UCSRA, UDRE);
+}
+
+
diff --git a/src/inc/uart/uart.h b/src/inc/uart/uart.h
new file mode 100755
index 0000000..6e24df5
--- /dev/null
+++ b/src/inc/uart/uart.h
@@ -0,0 +1,17 @@
+#ifndef UART_H
+#define UART_H
+  #include <util/setbaud.h>
+  #include <avr/interrupt.h>
+
+  /// #define STRING_SIZE 32
+  /// typedef struct
+  /// {
+    /// char data[STRING_SIZE];
+    /// int8_t size;
+  /// } string;
+  /// volatile string uart_string;
+
+  void uart_init();
+  void uart_putc(char c);
+
+#endif
-- 
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