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authorMax Christian Pohle2015-07-27 15:12:22 +0200
committerMax Christian Pohle2015-07-27 15:12:22 +0200
commit2df2697107d7873232c31a25a6947711b0903edb (patch)
treeff7247e9e970c69f3d3385950b19db9997a511b8 /src/inc
downloadalarmclock-2df2697107d7873232c31a25a6947711b0903edb.tar.bz2
alarmclock-2df2697107d7873232c31a25a6947711b0903edb.zip
latest running version from march 2011, not having been in repo before,
dcf77 working, mp3 playback and two display types are supported
Diffstat (limited to 'src/inc')
-rwxr-xr-xsrc/inc/int/dcf77/clock.c157
-rwxr-xr-xsrc/inc/int/dcf77/clock.h98
-rwxr-xr-xsrc/inc/pwm/pwm.c13
-rwxr-xr-xsrc/inc/pwm/pwm.h3
-rwxr-xr-xsrc/inc/spi/dev/audio_vs1011.c173
-rwxr-xr-xsrc/inc/spi/dev/audio_vs1011.h91
-rwxr-xr-xsrc/inc/spi/dev/display_dogm.c39
-rwxr-xr-xsrc/inc/spi/dev/display_dogm.h31
m---------src/inc/spi/dev/petit0
-rwxr-xr-xsrc/inc/spi/spi.c56
-rwxr-xr-xsrc/inc/spi/spi.h37
-rwxr-xr-xsrc/inc/stdalg.c29
-rwxr-xr-xsrc/inc/stdalg.h8
-rwxr-xr-xsrc/inc/stdout.c154
-rwxr-xr-xsrc/inc/stdout.h41
-rwxr-xr-xsrc/inc/uart/uart.c47
-rwxr-xr-xsrc/inc/uart/uart.h17
17 files changed, 994 insertions, 0 deletions
diff --git a/src/inc/int/dcf77/clock.c b/src/inc/int/dcf77/clock.c
new file mode 100755
index 0000000..75f33fe
--- /dev/null
+++ b/src/inc/int/dcf77/clock.c
@@ -0,0 +1,157 @@
1#include "clock.h"
2
3
4// returns -1 on error
5unsigned char getBits(const DCF start, const char len, const DCF pbit)
6{
7 static const unsigned char mult[] = {1, 2, 4, 8, 10, 20 ,40 ,80};
8 /// unsigned char p = 1; //parity
9 unsigned char r = 0; // retval
10 unsigned char i;
11 for(i=0; i<len; i++)
12 {
13 r += dcf77[start+i].bit * mult[i];
14 /// if(dcf77[start+i].bit)
15 /// p ^= 1;
16 }
17
18 // 1110011
19 // 001000
20
21 // 8
22 // 72
23
24 /// if((pbit != DCF_FIRST) && (dcf77[pbit].bit != p))
25 /// return -1;
26 /// else
27 return r;
28}
29
30void set_dcf_value()
31{
32 // check for parity
33 /// if
34 /// (
35 /// (dcf77[DCF_FIRST].bit != 0 ) |
36 /// (dcf77[DCF_START].bit != 1 ) |
37 /// (getBits(DCF_MIN, 7, DCF_MINP) == -1) |
38 /// (getBits(DCF_MIN, 7, DCF_START) > 59) |
39 /// (getBits(DCF_HOUR, 6, DCF_HOURP) == -1)
40 /// ) return;
41
42 // set new time
43 t_current.m = (getBits(DCF_MIN, 7, DCF_START)) - 1;
44 t_current.h = (getBits(DCF_HOUR, 6, DCF_START));
45 t_current.dd = (getBits(DCF_DAY, 6, DCF_START));
46 t_current.wd = (getBits(DCF_WEEKDAY, 3, DCF_START));
47 t_current.mm = (getBits(DCF_MONTH, 5, DCF_START));
48 t_current.yy = (getBits(DCF_YEAR, 8, DCF_START));
49}
50
51// 7372800/a=10000
52// 115200 / a * x = 10000
53// 7372800/8/150
54ISR(TIMER0_COMP_vect) // called 10000 times per second (12000000/8/150)
55{
56 //cli();
57 // F_CPU / PRESCALER / (OCR0 + 1)
58 if(++t_current.us >= 10) // one u-second
59 {
60 t_current.us = 0; // restart
61 // interval length of dcf77 can be greater than 1000 ms... count it!
62 ++interval;
63
64 /*
65 cli();
66 if(t_current.ms <= 500)
67 { OCR1A = 50 + (200 - (t_current.ms / 3)); }
68 else
69 { OCR1A = 50 + (200 - ((1000 - t_current.ms) / 3)); }
70 sei();
71 */
72
73 if(++t_current.ms >= 1000) // one second
74 {
75 t_current.ms = 0; // restart
76 if(++t_current.s > 59) // one minute
77 {
78 t_current.s = 0; // restart
79 if(++t_current.m > 59) // one hour
80 {
81 t_current.m = 0; // restart
82 if(++t_current.h > 23) // one day
83 {
84 t_current.h = 0; // restart
85 t_current.dd++;
86 }
87 }
88 }
89 }
90 }
91 //sei();
92}
93
94ISR(INT0_vect)
95{
96 /// stdout_put_int(interval, uart_putc);
97 /// stdout_put_string("INT0 call\n", uart_putc);
98 cli();
99 if(INT0_CONTROL == INT0_RISING_EDGE)
100 {
101 if(interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
102 {
103 /// if(dcf77_bit == 59) // check if every bit has been transfered
104 set_dcf_value(); // completely received- apply new time data
105
106 // 59th second: synchronize with receiver...
107 dcf77_bit = 0;
108 TCNT0 = 0;
109 t_current.s = 0;
110 t_current.ms = 0;
111 t_current.us = 0;
112 }
113 INT0_CONTROL = INT0_FALLING_EDGE;
114 }
115 else // INT0_FALLING_EDGE
116 {
117 dcf77[dcf77_bit++].bit = interval >= 200 ? 1 : 0;
118 lastinterval = interval;
119
120 INT0_CONTROL = INT0_RISING_EDGE;
121 }
122
123 interval = 0; // reset interval to count next interval
124 sei();
125}
126
127
128void timer_init()
129{
130 // 7372800/8
131 DDRD &= ~((1<<PD2) | (1<<PD3)); // make INT0 and INT1 input-pins
132
133 // Prescaler...
134 TCCR0 = (0<<CS02) | (1<<CS01) | (0<<CS00) | (1<<WGM01);
135 // output compare...
136 OCR0 = 149;
137 //OCR0 = 152 - 1;
138 //TCCR0 |= (0<<WGM01) | (1<<WGM01);
139
140 // ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
141 // ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
142 // CSx: set prescaler (010 means 8)
143 /// TCCR1B = (1<<ICNC1) | (1<<ICES1) | (0<<CS12) | (1<<CS11) | (0<<CS10);
144 // OCIE0: Output Compare Match Interrupt Enable
145 // TICIE: Timer/Counter Input Capture Interrupt Enable
146 TIMSK |= (1<<OCIE0);
147
148 // interrupts_init...
149 // General Interrupt Mask Register (enables interrupts)
150 //GIMSK |= (1<<INT0);
151 GICR |= (1<<INT0);
152 // MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
153 //MCUCR |= (0<<ISC01) | (1<<ISC00); // any logical change generates interrupt
154 INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
155 /// loworhigh.bit = 0;
156}
157
diff --git a/src/inc/int/dcf77/clock.h b/src/inc/int/dcf77/clock.h
new file mode 100755
index 0000000..c7f75c7
--- /dev/null
+++ b/src/inc/int/dcf77/clock.h
@@ -0,0 +1,98 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3 /* this dcf77-module relies on a accuarate clock (cristal) for receiving
4 * the dcf-signal. therefor the clock is going to work as expected,
5 * even with no dcf77-signal available.
6 * receivement is automatically turned on, if the avr is connected to the
7 * signal via INT0. if there is no signal the clock will not be set (K.I.S.S.)
8 *
9 */
10 #include <stdint.h>
11 #include <avr/io.h>
12 #include <avr/interrupt.h>
13 #include <limits.h>
14
15 /// #include "../stdout.h"
16 /// #include "../display/display.h"
17 /// #include "../uart/uart.h"
18
19 #define INT0_CONTROL MCUCR
20 #define INT0_FALLING_EDGE 0x02
21 #define INT0_RISING_EDGE 0x03
22
23
24
25 typedef struct
26 {
27 volatile unsigned char bit : 1;
28 } Bit;
29
30 typedef struct
31 {
32 unsigned char h ; // hour
33 unsigned char m ; // minute
34 unsigned char s ; // second
35 unsigned char dd; // day
36 unsigned char wd; // weekday
37 unsigned char mm; // month
38 unsigned char yy; // year
39 unsigned char us; // 10th second
40 unsigned int ms; // milli second
41 } Time;
42
43 typedef enum
44 {
45 DCF_FIRST = 0, // start of a new minute (note: always 0)
46 DCF_WEATHER = 14, // proprietary :-(
47 DCF_ANTENNA = 15, // 0: normal, 1: replacement
48 DCF_DST = 16, // daylight saving time: this hour new time...
49 DCF_MEZ = 17, // 'summer-time'
50 DCF_MESZ = 18, // 'winter-time'
51 DCF_DBLSEC = 19, // one extra second gonna be inserted
52 DCF_START = 20, // begin of time-info (note: always 1)
53 DCF_MIN = 21, // 7 bit
54 DCF_MINP = 28, // parity bit for minutes
55 DCF_HOUR = 29, // 6 bit
56 DCF_HOURP = 35, // parity bit for hours
57 DCF_DAY = 36, // 6 bit
58 DCF_WEEKDAY = 42, // 3 bit
59 DCF_MONTH = 45, // 5 bit
60 DCF_YEAR = 50, // 8 bit
61 DCF_DATEP = 58 // parity bit for date
62 } DCF;
63
64 /*
65 typedef struct
66 {
67 Bit useless[14];
68 Bit antenna;
69 Bit dst;
70 Bit mez;
71 Bit mesz;
72 Bit dblsec;
73 Bit start; // < always 1 - use for verification
74 unsigned char min : 7;
75 Bit min_p; // < minutes parity
76 unsigned char hour : 6;
77 Bit hour_p; // < hours parity
78 unsigned char day : 6; // day of month
79 unsigned char dow : 3; // day of week (1=monday)
80 unsigned char month : 5; // month of year
81 unsigned char year : 8; // year
82 Bit date_p; // parity of date
83 } DCF_Signal;
84 */
85
86
87 volatile Bit dcf77[60];
88 volatile unsigned char dcf77_bit;
89 volatile Time t_current;
90 volatile unsigned int interval;
91 volatile unsigned int lastinterval;
92
93 /// void getBits(volatile unsigned char* target, const DCF start, const char len, const DCF parity);
94 /// void set_dcf_value();
95 void timer_init();
96 /// void interrupts_init();
97
98#endif
diff --git a/src/inc/pwm/pwm.c b/src/inc/pwm/pwm.c
new file mode 100755
index 0000000..fac9347
--- /dev/null
+++ b/src/inc/pwm/pwm.c
@@ -0,0 +1,13 @@
1
2void pwminit()
3{
4 TCCR0 |= (1<<WGM01);
5}
6
7void pwm_setInterval()
8{
9 /// if(t_current.ms <= 500)
10 /// { OCR1A = 50 + (200 - (t_current.ms / 3)); }
11 /// else
12 /// { OCR1A = 50 + (200 - ((1000 - t_current.ms) / 3)); }
13}
diff --git a/src/inc/pwm/pwm.h b/src/inc/pwm/pwm.h
new file mode 100755
index 0000000..8b671bc
--- /dev/null
+++ b/src/inc/pwm/pwm.h
@@ -0,0 +1,3 @@
1#include <avr/io.h>
2
3void pwminit();
diff --git a/src/inc/spi/dev/audio_vs1011.c b/src/inc/spi/dev/audio_vs1011.c
new file mode 100755
index 0000000..ad44654
--- /dev/null
+++ b/src/inc/spi/dev/audio_vs1011.c
@@ -0,0 +1,173 @@
1#include "audio_vs1011.h"
2/// inline void audio_vs1011_setVolume(unsigned char left, unsigned char right)
3/// { audio_vs1011_cmd(SCI_VOL, left, right); }
4
5void audio_vs1011_init()
6{
7 // [initialize pins and ports]
8 DDRC |= ((1<<PC1) | (1<<PC2) | (1<<PC4)); // XCS/XDCS/RESET
9 DDRC &= ~(1<<PC3); // DREQ
10 //DDRA |= (1<<PA6); // activate O-Port A6 as [XCS]
11 //DDRC |= (1<<PC6); // activate O-Port C6 as [XDCS]
12 //DDRD |= (1<<PD6); // activate O-Port D6 as [RESET]
13 //DDRD &= ~(1<<PD5); // activate I-Port D5 as [DREQ]
14
15
16 // pins...
17 /// PORTA |= (1<<PA6);
18 /// PORTC |= (1<<PC6);
19 PORTC |= (1<<PC3); // enable pullup resistor for [DREQ]
20 audio_vs1011_exit_xcs(); // activate XCS: deactivate vs1011-cmd-line
21 audio_vs1011_exit_xdcs(); // activate XDCS: deactivate vs1011-data-line
22
23 // [reset vs1011]
24 // this ensures, that it finds XCS and XDCS in proper state (see below)
25 /// PORTD &= ~(1<<PD6); // <reset>
26 // Wait for at least 10 ms after startup (required!!)
27 // then make GPIO an output signal and set it to 1...
28 /// _delay_ms(20);
29 PORTC |= (1<<PC4); // </reset>
30 /// _delay_ms(20);
31
32 // wait until DREQ is set- so chip has rebooted from reset...
33 wait4dreq();
34
35 // [set vs1011 to 'new-mode']
36 // where xdcs is driven low, before you want to send mp3-data or test-bits
37 // where xcs is driven low to send SCI-commands.
38 // and both together may not been activated, why we started with resetting
39 // after having configured those output-ports.
40 audio_vs1011_cmd(SCI_MODE, (SM_SDINEW | SM_TESTS));
41
42 // [set clock-frequency...]
43 // formular:
44 // 32768{if clock doubler}
45 // + (F_CRYSTAL{crystals frequency in Hz} / 2000{const})
46 // = 0x9770 for a 12MHz-crystal (with clock-doubler), so send:
47 /// audio_vs1011_cmd(SCI_CLOCKF, 0x98, 0x00);
48 /// stdout_put_uint(uart_putc, ((F_CPU / 2000) | SC_CLK2X));
49 /// stdout_put_string(uart_putc, "\t< clock freq for vs1011\n");
50
51 audio_vs1011_cmd(SCI_CLOCKF, ((F_CPU / 2000) | SC_CLK2X));
52 audio_vs1011_cmd(SCI_AUDATA, 44100);
53
54 /*
55 spi_setspeed(SPICLK_FAST);
56 int q;
57 for(q=0; q<=30000; q++)
58 spi_putc(0x00);
59 spi_setspeed(SPICLK_DEFAULT);
60 // wait for at least 11000 clock cycles...
61 */
62
63 // wait until DREQ is set- so chip has rebooted from reset...
64 wait4dreq();
65
66
67 /// spi_putc(0xFF);
68
69 audio_vs1011_setVolume(1, 1); // left and right both to 100%=0xFF
70 /// _delay_ms(250);
71
72 /// stdout_put_string(uart_putc, "clock frequency set!\n");
73}
74
75
76void audio_vs1011_setVolume(const unsigned char left, const unsigned char right)
77{
78 //uint16_t volume = right + (256 * left);
79 /// stdout_put_uint(uart_putc, volume);
80 /// stdout_put_string(uart_putc, "\t< new volume for vs1011\n");
81 audio_vs1011_cmd(SCI_VOL, ((uint16_t) right) + ((uint16_t) left * 256));
82}
83
84void audio_vs1011_test_volume()
85{
86 audio_vs1011_setVolume(0, 0); // left and right to 0%=0x00 -> standby
87 _delay_ms(250);
88 audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
89 _delay_ms(250);
90}
91
92void audio_vs1011_test_sine()
93{
94 static const unsigned char sinetest[] = {0x53, 0xEF, 0x6E, 0x30, 0x0, 0x0, 0x0, 0x0};
95 static const unsigned char testexit[] = {'E', 'x', 'i', 't', 0x0, 0x0, 0x0, 0x0};
96
97 /// audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
98 /// stdout_put_string(uart_putc, "activating sine-test...\n");
99 audio_vs1011_dat(sinetest, sizeof(sinetest));
100 _delay_ms(250);
101
102 /// stdout_put_string(uart_putc, "deactivating sine-test...\n");
103 audio_vs1011_dat(testexit, sizeof(testexit));
104 _delay_ms(250);
105 /// audio_vs1011_setVolume(255, 255); // left and right both to 100%=0xFF
106}
107
108/*
109void audio_vs1011_test_eeprom()
110{
111 unsigned char block[512];
112 eeprom_read_block((void*) &block, (const void*) 0, 512);
113
114 int i,q;
115 for(i=0; i<512; i+=32)
116 {
117 audio_vs1011_enable();
118 loop_until_bit_is_set(PIND, PD5);
119 for(q=0; q<32; q++)
120 spi_putc(block[i+q]);
121 audio_vs1011_disable();
122 }
123 loop_until_bit_is_set(PIND, PD5);
124 _delay_ms(500);
125}
126*/
127
128void audio_vs1011_dat(const unsigned char* dat, const unsigned char size)
129{
130 audio_vs1011_enable();
131 unsigned char i;
132 for(i=0; i<size; i++)
133 spi_putc(dat[i]);
134 audio_vs1011_disable();
135}
136
137
138/*
139unsigned char audio_vs1011_stream(unsigned char (*readfn)())
140{
141 audio_vs1011_enable();
142 register unsigned char i;
143 for(i=0; i<32; i++)
144 spi_putc(readfn());
145 audio_vs1011_disable();
146 audio_vs1011_waitDREQ();
147 return 32;
148}*/
149
150
151
152
153void audio_vs1011_cmd(const unsigned char cmd, uint16_t dat)
154{
155 loop_until_bit_is_set(PIND, PD5);
156 /// audio_vs1011_enable();
157 //PORTA &= ~(1<<PA6); // <XCS>
158 audio_vs1011_init_xcs();
159 spi_putc(VS_WRITE);
160 spi_putc(cmd);
161 spi_putc((dat >> 8) & 0xFF);
162 spi_putc((dat >> 0) & 0xFF);
163 //PORTA |= (1<<PA6); // </XCS>
164 audio_vs1011_exit_xcs();
165 spi_putc(0);
166 spi_putc(0);
167 spi_putc(0);
168 spi_putc(0);
169 /// audio_vs1011_disable();
170 /// _delay_ms(1); // << wait to make sure vs1011 got the message
171 _delay_ms(5);
172 loop_until_bit_is_set(PIND, PD5); // << wait for DREQ to become ready again
173}
diff --git a/src/inc/spi/dev/audio_vs1011.h b/src/inc/spi/dev/audio_vs1011.h
new file mode 100755
index 0000000..ec97550
--- /dev/null
+++ b/src/inc/spi/dev/audio_vs1011.h
@@ -0,0 +1,91 @@
1#ifndef AUDIO_VS1011_H
2#define AUDIO_VS1011_H
3
4 #include <avr/io.h>
5 #include <util/delay.h>
6 #include <inttypes.h>
7 #include <avr/eeprom.h>
8
9 #include "../spi.h"
10 /// #include "../../uart/uart.h"
11 /// #include "../../stdout.h"
12
13
14 #define audio_vs1011_enable() PORTC &= ~(1<<PC6); // <XDCS>
15 #define audio_vs1011_disable() PORTC |= (1<<PC6); // </XDCS>
16 #define audio_vs1011_isDREQ() (PIND & (1<<PD5))
17 #define audio_vs1011_waitDREQ(); loop_until_bit_is_set(PIND, PD5);
18
19
20 // [OPERATIONS]
21 #define VS_WRITE 0x2
22 #define VS_READ 0x3
23
24
25 // [SCI REGISTERS] - page 29
26 #define SCI_MODE 0x0 // Mode control
27 #define SCI_STATUS 0x1 // Status of VS1011e
28 #define SCI_BASS 0x2 // Built-in bass/treble enhancer
29 #define SCI_CLOCKF 0x3 // Clock freq + multiplier
30 #define SCI_DECODE_TIME 0x4 // Decode time in seconds
31 #define SCI_AUDATA 0x5 // Misc. audio data
32 #define SCI_WRAM 0x6 // RAM write/read
33 #define SCI_WRAMADDR 0x7 // Base address for RAM write/read
34 #define SCI_HDAT0 0x8 // Stream header data 0
35 #define SCI_HDAT1 0x9 // Stream header data 1
36 #define SCI_AIADDR 0xA // Start address of application
37 #define SCI_VOL 0xB // Volume control
38 #define SCI_AICTRL0 0xC // Application control register 0
39 #define SCI_AICTRL1 0xD // Application control register 1
40 #define SCI_AICTRL2 0xE // Application control register 2
41 #define SCI_AICTRL3 0xF // Application control register 3
42
43 // [VALUES::SCI_MODE]
44 #define SM_DIFF 0x1 // Differential
45 #define SM_LAYER12 0x2 // Allow MPEG layers I & II
46 #define SM_RESET 0x4 // Soft reset
47 #define SM_OUTOFWAV 0x8 // Jump out of WAV decoding
48 #define SM_SETTOZERO1 0x10 // set to zero
49 #define SM_TESTS 0x20 // Allow SDI tests
50 #define SM_STREAM 0x40 // Stream mode
51 #define SM_SETTOZERO2 0x80 // set to zero
52
53 #define SM_DACT 0x100 // DCLK active edge
54 #define SM_SDIORD 0x200 // SDI bit order
55 #define SM_SDISHARE 0x400 // Share SPI chip select
56 #define SM_SDINEW 0x800 // VS1002 native SPI modes
57 #define SM_SETTOZERO3 0x1000 // set to zero
58
59 // [VALUES::SCI_CLOCKF]
60 #define SC_CLK2X 0x8000 // clock doubler
61
62 #define audio_vs1011_init_xcs() PORTC &= ~(1<<PC1) // <XCS>
63 #define audio_vs1011_exit_xcs() PORTC |= (1<<PC1); // </XCS>
64
65 #define audio_vs1011_init_xdcs() PORTC &= ~(1<<PC2) // <XCS>
66 #define audio_vs1011_exit_xdcs() PORTC |= (1<<PC2); // </XCS>
67
68 #define wait4dreq() loop_until_bit_is_set(PINC, PC3); // <DREQ></DREQ>
69
70
71 /// void audio_vs1011_cmd(const unsigned char sci_cmd, const unsigned char hdata,
72 /// const unsigned char ldata);
73 void audio_vs1011_init();
74 void audio_vs1011_cmd(const unsigned char cmd, uint16_t dat);
75 void audio_vs1011_setVolume(const unsigned char left, const unsigned char right);
76
77 //void audio_vs1011_dat(const unsigned char dat[32]);
78 void audio_vs1011_dat(const unsigned char* dat, const unsigned char size);
79 /// unsigned char audio_vs1011_stream(unsigned char (*readfn)());
80 void audio_vs1011_test_sine();
81 void audio_vs1011_test_volume();
82 /// void audio_vs1011_test_eeprom();
83 /// void audio_vs1011_enable();
84 /// void audio_vs1011_disable();
85 /// char audio_vs1011_isDREQ();
86
87
88 /// void audio_vs1011_test_softreset();
89
90
91#endif
diff --git a/src/inc/spi/dev/display_dogm.c b/src/inc/spi/dev/display_dogm.c
new file mode 100755
index 0000000..a655769
--- /dev/null
+++ b/src/inc/spi/dev/display_dogm.c
@@ -0,0 +1,39 @@
1#include "display_dogm.h"
2
3void display_dogm_init()
4{
5 //DDRA |= (1<<PA7); // activate portA for display
6 //DDRC |= (1<<PC7); // activate portC for display
7 DDRD |= (1<<PD7) | (1<<PD6);
8 PORTD |= (1<<PD7) | (1<<PD6);
9
10 // Wait time >40mS after VDD stable
11 _delay_ms(50); // 10ms for safty
12
13 display_dogm_exec(CMD_FUNCTION_SET);
14 display_dogm_exec(CMD_FUNCTION_SET);
15 display_dogm_exec(CMD_CONTRAST_SET);
16 display_dogm_exec(CMD_POWER_CONTROL);
17 display_dogm_exec(CMD_FOLLOWER_CONTROL);
18 display_dogm_exec(CMD_DISPLAY_ONOFF);
19 display_dogm_exec(CMD_ENTRY_MODE_SET);
20 display_dogm_exec(CMD_DISPLAY_CLEAR);
21}
22
23void display_dogm_putc(char c)
24{
25 PORTD &= ~(1<<PD7); // chip select: activate display
26 PORTD |= (1<<PD6); // L=Commandmode, H=Datamode
27 spi_putc(c);
28 _delay_us(40); // try and error value (you get chinese chars? increase!)
29 PORTD |= (1<<PD7); // chip select: deactivate display
30}
31
32void display_dogm_exec(char c)
33{
34 PORTD &= ~(1<<PD7); // chip select: activate display
35 PORTD &= ~(1<<PD6); // L=Commandmode, H=Datamode
36 spi_putc(c);
37 _delay_ms(4); // time the longest command takes on display
38 PORTD |= (1<<PD7); // chip select: deactivate display
39}
diff --git a/src/inc/spi/dev/display_dogm.h b/src/inc/spi/dev/display_dogm.h
new file mode 100755
index 0000000..d9cf560
--- /dev/null
+++ b/src/inc/spi/dev/display_dogm.h
@@ -0,0 +1,31 @@
1#ifndef DISPLAY_DOGM_H
2#define DISPLAY_DOGM_H
3
4 #include <avr/io.h>
5 #include <util/delay.h>
6 #include "../spi.h"
7
8 #define CONTAST 3
9
10 #define CMD_FUNCTION_SET 32 + 16 + 8 + 0 + 1
11 #define CMD_POWER_CONTROL 64 + 0 + 16 + 0 + 4 + CONTAST
12 #define CMD_FOLLOWER_CONTROL 0x6E
13
14 #define CMD_ENTRY_MODE_SET 4 + 2 + 0
15 #define CMD_DISPLAY_HOME 0 + 2 + 0
16 #define CMD_DISPLAY_CLEAR 0 + 0 + 1
17
18 #define CMD_CONTRAST_SET 0x7F
19 #define CMD_FUNCTION_SET2 0x38
20 #define CMD_DISPLAY_ONOFF 0x0C
21 #define CMD_DISPLAY_POS 0x80
22
23 //#define display_dogm_enable() PORTD &= ~(1<<PD7); PORTD |= (1<<PD6); // <XDCS>
24 //#define display_dogm_disable() PORTD |= (1<<PD7); PORTD &= ~(1<<PD6); // </XDCS>
25
26
27 void display_dogm_init();
28 void display_dogm_putc(char);
29 void display_dogm_exec(char);
30
31#endif
diff --git a/src/inc/spi/dev/petit b/src/inc/spi/dev/petit
new file mode 160000
Subproject b1109539d5d34b62849d67a65ce244fcb1d0f5e
diff --git a/src/inc/spi/spi.c b/src/inc/spi/spi.c
new file mode 100755
index 0000000..b04fe7e
--- /dev/null
+++ b/src/inc/spi/spi.c
@@ -0,0 +1,56 @@
1#include "spi.h"
2
3void spi_init()
4{
5 // setup SPI-Port
6 DDR_SPI = (1<<DD_MOSI) | (1<<DD_SS) | (1<<DD_SCK);
7 PORT_SPI |= (1<<DD_SS);
8
9 // SPI Control Register (SPCR)
10 // SPI Enable=1 | Data Order=LSB | SPI_Master=1 (!make SS stay HIGH!)
11 // SPCR |= (1<<SPE) | (1<<DORD) | (1<<MSTR) | (1<<CPOL) | (1<<CPHA) | (1<<SPR1) | (1<<SPR0);
12 // (1<<DORD) - would be LSB-mode (, but we need MSB-mode!)
13 SPCR = (1<<SPE) | (1<<MSTR); // (1<<SPR1) | (1<<SPR0)
14 spi_setspeed(SPICLK_DEFAULT);
15 // setup SPI options
16 /// SPSR &= ~(1<<SPI2X); // do not use SPI speed-doubler
17}
18
19void spi_setspeed(SPICLK speed)
20{
21 if(speed < 4) // nominal clock speeds
22 {
23 SPSR &= ~(1<<SPI2X); // do not use SPI speed-doubler
24 SPCR |= speed;
25 }
26 else // use SPI2X
27 {
28 SPSR |= (1<<SPI2X); // use SPI speed-doubler
29 SPCR |= (speed - 0x4);
30 }
31 _delay_ms(2);
32}
33
34void spi_putc(unsigned char c)
35{
36 /// uart_putc('>');
37 /// uart_putc(c);
38 /// uart_putc('\n');
39 SPDR = c;
40 loop_until_bit_is_set(SPSR, SPIF);
41 /// stdout_put_string(uart_putc, "- [done]\n");
42}
43
44unsigned char spi_getc()
45{
46 SPDR = 0xFF; // init receive register with value
47 /* Wait for reception complete */
48 while(!(SPSR & (1<<SPIF)));
49 /* Return data register */
50 return SPDR;
51 /// unsigned char c = SPDR;
52 /// uart_putc('<');
53 /// uart_putc(c);
54 /// uart_putc('\n');
55 /// return c;
56}
diff --git a/src/inc/spi/spi.h b/src/inc/spi/spi.h
new file mode 100755
index 0000000..bb92cac
--- /dev/null
+++ b/src/inc/spi/spi.h
@@ -0,0 +1,37 @@
1#ifndef SPI_H
2#define SPI_H
3
4 #include <avr/io.h>
5 #include <util/delay.h>
6 #include "../uart/uart.h"
7 #include "../stdout.h"
8
9 #define SPICLK_DEFAULT SPICLK_64
10 #define SPICLK_FAST SPICLK_X2
11
12 #define PORT_SPI PORTB
13 #define DDR_SPI DDRB
14 #define DD_SS DDB4
15 #define DD_MOSI DDB5
16 #define DD_MISO DDB6
17 #define DD_SCK DDB7
18
19 typedef enum
20 {
21 SPICLK_4, // vv nominal clk-speeds
22 SPICLK_16,
23 SPICLK_64,
24 SPICLK_128,
25 SPICLK_X2, // vv with SPI2x
26 SPICLK_X32,
27 SPICLK_X64
28 } SPICLK;
29
30
31 void spi_init();
32 void spi_putc(unsigned char c);
33 unsigned char spi_getc();
34 void spi_setspeed(SPICLK speed);
35
36
37#endif
diff --git a/src/inc/stdalg.c b/src/inc/stdalg.c
new file mode 100755
index 0000000..99558a9
--- /dev/null
+++ b/src/inc/stdalg.c
@@ -0,0 +1,29 @@
1#include "stdalg.h"
2
3#ifdef STDALGO_CRC7
4 unsigned char crc7(unsigned char* bytes, unsigned char size)
5 {
6 register unsigned char val = 0; // last cycles value
7 register unsigned char cb; // current byte.
8
9 unsigned char i;
10 for(i=0; i<=size; i++)
11 {
12 cb = bytes[i];
13
14 int q = (i==size) ? 7 : 8; // counter
15 do
16 {
17 val <<= 1;
18 if(cb & 0x80) // check MSB of current byte
19 ++val; // overflow, add 1
20
21 if(val & 0x80) // check MSB of (last) seed
22 val ^= 0x9; // polynome
23 cb <<= 1;
24 } while(--q);
25 val &= 0x7f; // lower 7 bits
26 }
27 return ((val<<1) + 1);
28 }
29#endif
diff --git a/src/inc/stdalg.h b/src/inc/stdalg.h
new file mode 100755
index 0000000..5f31cc5
--- /dev/null
+++ b/src/inc/stdalg.h
@@ -0,0 +1,8 @@
1#ifndef STDALG_H
2#define STDALG_H
3
4 #ifdef STDALGO_CRC7
5 unsigned char crc7(unsigned char* bytes, unsigned char size);
6 #endif
7
8#endif
diff --git a/src/inc/stdout.c b/src/inc/stdout.c
new file mode 100755
index 0000000..0160e0b
--- /dev/null
+++ b/src/inc/stdout.c
@@ -0,0 +1,154 @@
1#include "stdout.h"
2
3#ifdef STDOUT_put_string
4 void stdout_put_string(void (*putc)(char c), const char* s)
5 {
6 register unsigned char c;
7 while ((c=*s++))
8 putc(c);
9 }
10#endif
11
12#ifdef STDOUT_put_uint
13 void stdout_put_uint(void (*putc)(const char c), int n)
14 {
15 unsigned char i;
16 for(i=0; _devisor_ten[i]>n; i++);
17 int c=0;
18 for(; i<sizeof(_devisor_ten) / sizeof(int); i++)
19 {
20 for(c=0; (n - _devisor_ten[i]) < n; c++)
21 n -= _devisor_ten[i];
22 putc('0' + c);
23 }
24 /// // if processor has can devide this might be better:
25 /// register unsigned int d=1;
26 /// for(; d<n; d*=10);
27 /// for(d /= 10; d>0; n %= d, d /= 10)
28 /// putc('0' + (n / d));
29 }
30#endif
31
32#ifdef STDOUT_reverse_bits
33 char stdout_reverse_bits(unsigned char v)
34 {
35 unsigned char s = sizeof(v) * CHAR_BIT; // bit size; must be power of 2
36 unsigned char mask = ~0;
37 while ((s >>= 1) > 0)
38 {
39 mask ^= (mask << s);
40 v = ((v >> s) & mask) | ((v << s) & ~mask);
41 }
42 return v;
43 }
44#endif
45
46#ifdef STDOUT_put_binary
47 void stdout_put_binary(void (*putc)(const char c), const unsigned char data)
48 {
49 char i;
50 for(i=CHAR_BIT-1; i>=0; i--)
51 {
52 if(data & (1<<i))
53 putc('1');
54 else
55 putc('0');
56 }
57 }
58#endif
59
60#ifdef STDOUT_putf
61void stdout_putf(void (*putc)(const char c), const char* format, ...)
62{
63 va_list vl;
64 va_start(vl, format);
65
66 typedef union
67 {
68 char as_char : (sizeof(char) * CHAR_BIT);
69 int as_int : (sizeof(int) * CHAR_BIT);
70 uint32_t as_uint : (sizeof(int) * CHAR_BIT);
71 } va_data;
72 va_data data;
73
74 do
75 {
76 if(format[0] != '%')
77 putc(format[0]);
78 else
79 {
80 char f = '\0'; // fill-char for fixed width numbers (\0 means OFF)
81 switch((++format)[0])
82 {
83 case '%':
84 putc('%');
85 break;
86 case 'c':
87 putc(va_arg(vl, int));
88 break;
89 case '0':
90 if(f == '\0')
91 f = '0';
92 case '-':
93 if(f == '\0')
94 f = ' ';
95 case ' ':
96 case 'd':
97 {
98 int width = 0;
99 data.as_int = va_arg(vl, unsigned int);
100
101 if(data.as_int < 0)
102 {
103 putc('-');
104 width = -1;
105 data.as_int *= -1;
106 }
107 else if(format[0] == ' ')
108 putc(' ');
109
110 if(f != '\0')
111 {
112 // translate string with user-requested fixed length...
113 static const int _potences[] = {1, 10, 100, 1000};
114
115 int s = 0;
116 while((++format)[1] !='d' && format[0] >='0' && format[0] <='9')
117 s++;
118 for(; s>=0; --s)
119 width += _potences[sizeof(_potences) - s] * (format[-s] - '0');
120
121 // count numbers width in decimal-system...
122 for(s=10; s<data.as_int; s*=10, --width);
123
124 // remove trailing numbers and append spacechar if wanted...
125 for(; width>1; width--, putc(f)); // prepend whitespace-character[space]
126 }
127
128 stdout_put_uint(putc, data.as_uint);
129 if(format[0] != 'd')
130 ++format;
131 }
132 break;
133 case 's':
134 #ifdef STDOUT_put_string
135 stdout_put_string(putc, va_arg(vl, char*));
136 #else
137 va_arg(vl, int); // remove next argument
138 #endif
139 break;
140 case 'b':
141 #ifdef STDOUT_put_binary
142 data.as_int = va_arg(vl, int);
143 stdout_put_binary(putc, data.as_uint);
144 #else
145 va_arg(vl, int); // remove next argument
146 #endif
147 break;
148 }
149 }
150 }
151 while((++format)[0] != '\0');
152 return;
153}
154#endif
diff --git a/src/inc/stdout.h b/src/inc/stdout.h
new file mode 100755
index 0000000..da7027f
--- /dev/null
+++ b/src/inc/stdout.h
@@ -0,0 +1,41 @@
1#ifndef STDOUT_H
2#define STDOUT_H
3 #include <inttypes.h>
4 #include <limits.h>
5
6 #ifdef STDOUT_put_string
7 void stdout_put_string(void (*putc)(const char c), const char* s);
8 #endif
9
10 #ifdef STDOUT_put_uint
11 static const unsigned int _devisor_two[] =
12 {
13 /// 2147483648, 1073741824, 536870912, 268435456, 134217728, 67108864,
14 /// 33554432, 16777216, 8388608, 4194304, 2097152, 1048576, 524288, 262144,
15 /// 131072, 65536,
16 32768, 16384, 8192, 4096, 2048, 1024, 512, 256, 128, 64,
17 32, 16, 8, 4, 2, 1
18 };
19 static const unsigned int _devisor_ten[] =
20 {
21 /// 1000000000, 100000000, 10000000, 1000000, 100000,
22 10000, 1000, 100, 10, 1
23 };
24 void stdout_put_uint(void (*putc)(const char c), int n);
25 #endif
26
27 #ifdef STDOUT_put_binary
28 void stdout_put_binary(void (*putc)( const char c), const unsigned char data);
29 #endif
30
31 #ifdef STDOUT_reverse_bits
32 char stdout_reverse_bits(const unsigned char v);
33 #endif
34
35 #ifdef STDOUT_putf
36 #include <stdarg.h>
37 extern void dec_put_char(const char);
38 void stdout_putf(void (*putc)( const char c), const char* format, ...);
39 #endif
40
41#endif
diff --git a/src/inc/uart/uart.c b/src/inc/uart/uart.c
new file mode 100755
index 0000000..b2f1a59
--- /dev/null
+++ b/src/inc/uart/uart.c
@@ -0,0 +1,47 @@
1#include "uart.h"
2
3/// // UART-Receiver...
4/// ISR(USART_RXC_vect)
5/// {
6 /// unsigned char buffer;
7 /// buffer = UDR;
8 /// if(uart_string.size == -1) return;
9 /// if(buffer == '\n')
10 /// {
11 /// uart_string.data[uart_string.size] = '\0';
12 /// uart_string.size = -1;
13 /// }
14 /// else
15 /// {
16 /// uart_string.data[uart_string.size] = buffer;
17 /// if(++uart_string.size > STRING_SIZE)
18 /// { uart_string.size = 0; }
19 /// }
20/// }
21
22void uart_init()
23{
24 /// uart_string.size = 0;
25 /// uart_string.data[0] = '\0';
26
27 // activate UART TX // and RX...
28 UCSRB |= (1<<TXEN); // | (1<<RXEN) | (1<<RXCIE);
29 // Asynchron 8N1 ...
30 UCSRC |= (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0);
31
32 UBRRH = UBRRH_VALUE;
33 UBRRL = UBRRL_VALUE;
34 #if USE_2X
35 UCSRA |= (1 << U2X);
36 #else
37 UCSRA &= ~(1 << U2X);
38 #endif
39}
40
41void uart_putc(char c)
42{
43 UDR = c; /* schreibt das Zeichen x auf die Schnittstelle */
44 loop_until_bit_is_set(UCSRA, UDRE);
45}
46
47
diff --git a/src/inc/uart/uart.h b/src/inc/uart/uart.h
new file mode 100755
index 0000000..6e24df5
--- /dev/null
+++ b/src/inc/uart/uart.h
@@ -0,0 +1,17 @@
1#ifndef UART_H
2#define UART_H
3 #include <util/setbaud.h>
4 #include <avr/interrupt.h>
5
6 /// #define STRING_SIZE 32
7 /// typedef struct
8 /// {
9 /// char data[STRING_SIZE];
10 /// int8_t size;
11 /// } string;
12 /// volatile string uart_string;
13
14 void uart_init();
15 void uart_putc(char c);
16
17#endif
..