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authorMax Christian Pohle2017-06-05 16:24:20 +0200
committerMax Christian Pohle2017-06-05 16:24:20 +0200
commitacf1faceeeb6461bb3c8c8266507151193f649b1 (patch)
tree89623374c3ba4a9288d82f51505374ac4ad24d25 /software/inc/int
parent255dcc3f40ed28aeb3da883c34547ffa781dc749 (diff)
parente2b37ffacd2b3e76fd849fc046466568d5ac0779 (diff)
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Add 'software/' from commit 'e2b37ffacd2b3e76fd849fc046466568d5ac0779'
git-subtree-dir: software git-subtree-mainline: 255dcc3f40ed28aeb3da883c34547ffa781dc749 git-subtree-split: e2b37ffacd2b3e76fd849fc046466568d5ac0779
Diffstat (limited to 'software/inc/int')
-rwxr-xr-xsoftware/inc/int/dcf77.c123
-rwxr-xr-xsoftware/inc/int/dcf77.h68
2 files changed, 191 insertions, 0 deletions
diff --git a/software/inc/int/dcf77.c b/software/inc/int/dcf77.c
new file mode 100755
index 0000000..31f1663
--- /dev/null
+++ b/software/inc/int/dcf77.c
@@ -0,0 +1,123 @@
1// vim:set et sw=2 ts=2 tw=120:
2#include "dcf77.h"
3
4// 7372800/a=10000
5// 115200 / a * x = 10000
6// 7372800/8/150
7
8// returns -1 on error
9unsigned char getBits(const DCF start, const char len)
10{
11 static const unsigned char mult[] = {1, 2, 4, 8, 10, 20, 40, 80};
12 /// unsigned char p = 1; //parity
13 unsigned char r = 0; // retval
14 unsigned char i;
15 for(i=0; i<len; i++)
16 r += dcf77[start+i].bit * mult[i];
17 /// if(dcf77[start+i].bit)
18 /// p ^= 1;
19 return r;
20}
21
22// interrupt service routine (ISR) for timer 0 A compare match
23ISR(TIMER0_COMPB_vect)
24{
25
26}
27
28// ISR(TIMER0A_COMP_vect)
29ISR(TIMER0_COMPA_vect)
30{
31 interval++;
32 if (++t_current.ms >= 1000) // one second
33 {
34 t_current.ms = 0; // restart
35 if (++t_current.s > 59) // one minute
36 {
37 t_current.s = 0; // restart
38 if (++t_current.m > 59) // one hour
39 {
40 t_current.m = 0; // restart
41 if (++t_current.h > 23) // one day
42 {
43 t_current.h = 0; // restart
44 t_current.dd++;
45 }
46 }
47 }
48 }
49}
50
51ISR(INT0_vect)
52{
53}
54
55ISR(PCINT0_vect)
56{
57 // if(INT0_CONTROL == INT0_RISING_EDGE)
58 // if(MCUCR & (1<<ISC00))
59 // {
60 if (interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
61 {
62 if(dcf77_bit == 59) // check if every bit has been transfered
63 {
64 t_current.m = getBits(DCF_MIN, 7);
65 t_current.h = getBits(DCF_HOUR, 6);
66 t_current.dd = getBits(DCF_DAY, 6);
67 t_current.wd = getBits(DCF_WEEKDAY, 3);
68 t_current.mm = getBits(DCF_MONTH, 5);
69 t_current.yy = getBits(DCF_YEAR, 8);
70 }
71
72 // 59th second: synchronize with receiver...
73 dcf77_bit = 0;
74 t_current.s = 0;
75 t_current.ms = 0;
76
77 // falling edge causes interrupt...
78 // INT0_CONTROL = INT0_FALLING_EDGE;
79 }
80 else // INT0_FALLING_EDGE
81 {
82 if(interval > 50 && interval < 150)
83 dcf77[dcf77_bit++].bit = 0;
84 else if(interval > 150 && interval < 250)
85 dcf77[dcf77_bit++].bit = 1;
86
87 // rising edge causes interrupt...
88 // INT0_CONTROL = INT0_RISING_EDGE;
89 }
90
91 TCNT0 = 0;
92 interval = 0;
93}
94
95/*
96void timer_init()
97{
98 // 7372800/8
99 // >>>>>> DDRD &= ~((1<<PD2) | (1<<PD3)); // make INT0 and INT1 input-pins
100
101 // Prescaler...
102 // output compare...
103
104 //OCR0 = 152 - 1;
105 //TCCR0 |= (0<<WGM01) | (1<<WGM01);
106
107 // ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
108 // ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
109 // CSx: set prescaler (010 means 8)
110 /// TCCR1B = (1<<ICNC1) | (1<<ICES1) | (0<<CS12) | (1<<CS11) | (0<<CS10);
111 // OCIE0: Output Compare Match Interrupt Enable
112 // TICIE: Timer/Counter Input Capture Interrupt Enable
113
114 // interrupts_init...
115 // General Interrupt Mask Register (enables interrupts)
116 GIMSK |= (1<<INT0);
117 // GICR |= (1<<INT0);
118 // MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
119 MCUCR |= (1<<ISC01) | (1<<ISC00); // any logical change generates interrupt
120 INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
121 /// loworhigh.bit = 0;
122}
123*/
diff --git a/software/inc/int/dcf77.h b/software/inc/int/dcf77.h
new file mode 100755
index 0000000..2d79cdd
--- /dev/null
+++ b/software/inc/int/dcf77.h
@@ -0,0 +1,68 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3 /* this dcf77-module relies on a accuarate clock (crystal) for receiving
4 * the dcf-signal. therefor the clock is going to work as expected,
5 * even with no dcf77-signal available.
6 * receivement is automatically turned on, if the avr is connected to the
7 * signal via INT0. if there is no signal the clock will not be set (K.I.S.S.)
8 *
9 */
10 #include <avr/io.h>
11 #include <avr/interrupt.h>
12 #include <stdint.h>
13
14 #define INT0_CONTROL MCUCR
15 // #define INT0_FALLING_EDGE 0x02
16 // #define INT0_RISING_EDGE 0x03
17 #define INT0_FALLING_EDGE (1<<ISC01)
18 #define INT0_RISING_EDGE (1<<ISC01 | 1<<ISC00)
19 #define INT0_EDGE_ANY (1<<ISC00)
20
21 typedef struct
22 {
23 volatile unsigned char bit : 1;
24 } Bit;
25
26 typedef struct
27 {
28 uint16_t h; // hour
29 uint16_t m; // minute
30 uint16_t s; // second
31 uint16_t ms; // milli second
32 uint8_t yy; // year
33 uint8_t mm; // month
34 uint8_t dd; // day
35 uint8_t wd; // weekday
36 } Time;
37
38 typedef enum
39 {
40 DCF_FIRST = 0, // start of a new minute (note: always 0)
41 DCF_WEATHER = 14, // proprietary :-(
42 DCF_ANTENNA = 15, // 0: normal, 1: replacement
43 DCF_DST = 16, // daylight saving time: this hour new time...
44 DCF_MEZ = 17, // 'summer-time'
45 DCF_MESZ = 18, // 'winter-time'
46 DCF_DBLSEC = 19, // one extra second gonna be inserted
47 DCF_START = 20, // begin of time-info (note: always 1)
48 DCF_MIN = 21, // 7 bit
49 DCF_MINP = 28, // parity bit for minutes
50 DCF_HOUR = 29, // 6 bit
51 DCF_HOURP = 35, // parity bit for hours
52 DCF_DAY = 36, // 6 bit
53 DCF_WEEKDAY = 42, // 3 bit
54 DCF_MONTH = 45, // 5 bit
55 DCF_YEAR = 50, // 8 bit
56 DCF_DATEP = 58 // parity bit for date
57 } DCF;
58
59 volatile Bit dcf77[60];
60 volatile uint8_t dcf77_bit;
61 volatile Time t_current;
62 volatile uint16_t interval;
63
64 /// void getBits(volatile unsigned char* target, const DCF start, const char len, const DCF parity);
65 /// void set_dcf_value();
66 /// void interrupts_init();
67
68#endif
..