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-rw-r--r--gEDA/_TRASH/version01/binary-watch7.new.pcb54
1 files changed, 54 insertions, 0 deletions
diff --git a/gEDA/_TRASH/version01/binary-watch7.new.pcb b/gEDA/_TRASH/version01/binary-watch7.new.pcb
new file mode 100644
index 0000000..dc7facc
--- /dev/null
+++ b/gEDA/_TRASH/version01/binary-watch7.new.pcb
@@ -0,0 +1,54 @@
1# release: pcb 1.99x
2# To read pcb files, the pcb version (or the cvs source date) must be >= the file version
3FileVersion[20070407]
4PCB["" 600000 500000]
5Grid[10000.000000 0 0 0]
6Cursor[0 0 0.000000]
7PolyArea[200000000.000000]
8Thermal[0.500000]
9DRC[1000 1000 1000 1000 1500 1000]
10Flags("nameonpcb,uniquename,clearnew,snappin")
11Groups("1,c:2:3:4:5:6,s:7:8")
12Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
13Element(0x00 "JUMPER2" "U1" "unknown" 0 0 3 100 0x00)
14(
15 Pin(50 50 60 38 "1" 0x101)
16 Pin(50 150 60 38 "2" 0x01)
17 ElementLine(0 0 0 200 10)
18 ElementLine(0 200 100 200 10)
19 ElementLine(100 200 100 0 10)
20 ElementLine(100 0 0 0 10)
21 ElementLine(0 100 100 100 10)
22 ElementLine(100 100 100 0 10)
23 Mark(50 50)
24)
25Layer(1 "top")
26(
27)
28Layer(2 "ground")
29(
30)
31Layer(3 "signal2")
32(
33)
34Layer(4 "signal3")
35(
36)
37Layer(5 "power")
38(
39)
40Layer(6 "bottom")
41(
42)
43Layer(7 "outline")
44(
45)
46Layer(8 "spare")
47(
48)
49Layer(9 "silk")
50(
51)
52Layer(10 "silk")
53(
54)
..