1 files changed, 139 insertions, 0 deletions
diff --git a/inc/int/dcf77.c b/inc/int/dcf77.c
new file mode 100755
index 0000000..13af50d
--- /dev/null
+++ b/inc/int/dcf77.c
@@ -0,0 +1,139 @@
+// vim:set et sw=2 ts=2 tw=120:
+#include "dcf77.h"
+// returns -1 on error
+unsigned char getBits(const DCF start, const char len)
+{
+  static const unsigned char mult[]  = {1, 2, 4, 8, 10, 20 ,40 ,80};
+  /// unsigned char p = 1; //parity
+  unsigned char r = 0; // retval
+  unsigned char i;
+  for(i=0; i<len; i++)
+    r += dcf77[start+i].bit * mult[i];
+    /// if(dcf77[start+i].bit)
+      /// p ^= 1;
+  return r;
+}
+void set_dcf_value()
+{
+  t_current.m = (getBits(DCF_MIN,      7)) - 1;
+  t_current.h = (getBits(DCF_HOUR,     6));
+  t_current.dd = (getBits(DCF_DAY,     6));
+  t_current.wd = (getBits(DCF_WEEKDAY, 3));
+  t_current.mm = (getBits(DCF_MONTH,   5));
+  t_current.yy = (getBits(DCF_YEAR,    8));
+}
+// 7372800/a=10000
+// 115200 / a * x = 10000
+// 7372800/8/150
+// interrupt service routine (ISR) for timer 0 A compare match
+/*
+ISR(TIMER0A_COMP_vect) // called 10000 times per second (12000000/8/150)
+{
+}
+*/
+ISR(TIMER0_COMPB_vect)
+{
+}
+ISR(TIMER0_COMPA_vect)
+{
+  interval++;
+  if (++t_current.ms >= 1000) // one second
+  {
+    t_current.ms = 0; // restart
+    if (++t_current.s > 59) // one minute
+    {
+      t_current.s = 0; // restart
+      if (++t_current.m > 59) // one hour
+      {
+        t_current.m = 0; // restart
+        if (++t_current.h > 23) // one day
+        {
+          t_current.h = 0; // restart
+          t_current.dd++;
+        }
+      }
+    }
+  }
+}
+ISR(INT0_vect)
+{
+}
+ISR(PCINT0_vect)
+{
+  interval = 1;
+  /// stdout_put_int(interval, uart_putc);
+  /// stdout_put_string("INT0 call\n", uart_putc);
+  // cli();
+  // if(INT0_CONTROL == INT0_RISING_EDGE)
+  // if(MCUCR & (1<<ISC00))
+  // {
+  if (interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
+  {
+    /// if(dcf77_bit == 59) // check if every bit has been transfered
+    // set_dcf_value();  // completely received- apply new time data
+    // 59th second: synchronize with receiver...
+    TCNT0 = 0;
+    dcf77_bit = 0;
+    t_current.s = 0;
+    t_current.ms = 0;
+    // t_current.us = 0;
+    // falling edge causes interrupt...
+    // MCUCR &= ~(1 << ISC00);
+    // MCUCR |=  (1 << ISC01);
+    // INT0_CONTROL = INT0_FALLING_EDGE;
+  }
+  else // INT0_FALLING_EDGE
+  {
+    dcf77[dcf77_bit++].bit = interval >= 200 ? 1 : 0;
+    // rising edge causes interrupt...
+    // MCUCR |= (1 << ISC00);
+    // MCUCR |= (1 << ISC01);
+    // INT0_CONTROL = INT0_RISING_EDGE;
+    // interval = 0; // reset interval to count next interval
+  }
+  interval = 0;
+  // sei();
+}
+/*
+void timer_init()
+{
+  // 7372800/8
+  // >>>>>> DDRD &= ~((1<<PD2) | (1<<PD3)); // make INT0 and INT1 input-pins
+  // Prescaler...
+  // output compare...
+  //OCR0   = 152 - 1;
+  //TCCR0 |= (0<<WGM01) | (1<<WGM01);
+  // ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
+  // ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
+  // CSx: set prescaler (010 means 8)
+  /// TCCR1B = (1<<ICNC1) | (1<<ICES1) | (0<<CS12) | (1<<CS11) | (0<<CS10);
+  // OCIE0: Output Compare Match Interrupt Enable
+  // TICIE: Timer/Counter Input Capture Interrupt Enable
+  // interrupts_init...
+  // General Interrupt Mask Register (enables interrupts)
+  GIMSK |= (1<<INT0);
+  // GICR |= (1<<INT0);
+  // MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
+  MCUCR |= (1<<ISC01) | (1<<ISC00); // any logical change generates interrupt
+  INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
+  /// loworhigh.bit = 0;
+}
+*/

diff --git a/inc/int/dcf77.c b/inc/int/dcf77.c new file mode 100755 index 0000000..13af50d --- /dev/null +++ b/inc/int/dcf77.c
@@ -0,0 +1,139 @@
	1	// vim:set et sw=2 ts=2 tw=120:
	2	#include "dcf77.h"
	3
	4	// returns -1 on error
	5	unsigned char getBits(const DCF start, const char len)
	6	{
	7	static const unsigned char mult[] = {1, 2, 4, 8, 10, 20 ,40 ,80};
	8	/// unsigned char p = 1; //parity
	9	unsigned char r = 0; // retval
	10	unsigned char i;
	11	for(i=0; i<len; i++)
	12	r += dcf77[start+i].bit * mult[i];
	13	/// if(dcf77[start+i].bit)
	14	/// p ^= 1;
	15	return r;
	16	}
	17
	18	void set_dcf_value()
	19	{
	20	t_current.m = (getBits(DCF_MIN, 7)) - 1;
	21	t_current.h = (getBits(DCF_HOUR, 6));
	22	t_current.dd = (getBits(DCF_DAY, 6));
	23	t_current.wd = (getBits(DCF_WEEKDAY, 3));
	24	t_current.mm = (getBits(DCF_MONTH, 5));
	25	t_current.yy = (getBits(DCF_YEAR, 8));
	26	}
	27
	28	// 7372800/a=10000
	29	// 115200 / a * x = 10000
	30	// 7372800/8/150
	31
	32	// interrupt service routine (ISR) for timer 0 A compare match
	33	/*
	34	ISR(TIMER0A_COMP_vect) // called 10000 times per second (12000000/8/150)
	35	{
	36
	37	}
	38	*/
	39	ISR(TIMER0_COMPB_vect)
	40	{
	41
	42	}
	43
	44	ISR(TIMER0_COMPA_vect)
	45	{
	46	interval++;
	47	if (++t_current.ms >= 1000) // one second
	48	{
	49	t_current.ms = 0; // restart
	50	if (++t_current.s > 59) // one minute
	51	{
	52	t_current.s = 0; // restart
	53	if (++t_current.m > 59) // one hour
	54	{
	55	t_current.m = 0; // restart
	56	if (++t_current.h > 23) // one day
	57	{
	58	t_current.h = 0; // restart
	59	t_current.dd++;
	60	}
	61	}
	62	}
	63	}
	64	}
	65
	66	ISR(INT0_vect)
	67	{
	68	}
	69
	70	ISR(PCINT0_vect)
	71	{
	72	interval = 1;
	73	/// stdout_put_int(interval, uart_putc);
	74	/// stdout_put_string("INT0 call\n", uart_putc);
	75	// cli();
	76
	77	// if(INT0_CONTROL == INT0_RISING_EDGE)
	78	// if(MCUCR & (1<<ISC00))
	79	// {
	80	if (interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
	81	{
	82	/// if(dcf77_bit == 59) // check if every bit has been transfered
	83	// set_dcf_value(); // completely received- apply new time data
	84
	85	// 59th second: synchronize with receiver...
	86	TCNT0 = 0;
	87	dcf77_bit = 0;
	88	t_current.s = 0;
	89	t_current.ms = 0;
	90	// t_current.us = 0;
	91	// falling edge causes interrupt...
	92	// MCUCR &= ~(1 << ISC00);
	93	// MCUCR \|= (1 << ISC01);
	94	// INT0_CONTROL = INT0_FALLING_EDGE;
	95	}
	96	else // INT0_FALLING_EDGE
	97	{
	98	dcf77[dcf77_bit++].bit = interval >= 200 ? 1 : 0;
	99
	100	// rising edge causes interrupt...
	101	// MCUCR \|= (1 << ISC00);
	102	// MCUCR \|= (1 << ISC01);
	103	// INT0_CONTROL = INT0_RISING_EDGE;
	104	// interval = 0; // reset interval to count next interval
	105	}
	106
	107	interval = 0;
	108	// sei();
	109	}
	110
	111	/*
	112	void timer_init()
	113	{
	114	// 7372800/8
	115	// >>>>>> DDRD &= ~((1<<PD2) \| (1<<PD3)); // make INT0 and INT1 input-pins
	116
	117	// Prescaler...
	118	// output compare...
	119
	120	//OCR0 = 152 - 1;
	121	//TCCR0 \|= (0<<WGM01) \| (1<<WGM01);
	122
	123	// ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
	124	// ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
	125	// CSx: set prescaler (010 means 8)
	126	/// TCCR1B = (1<<ICNC1) \| (1<<ICES1) \| (0<<CS12) \| (1<<CS11) \| (0<<CS10);
	127	// OCIE0: Output Compare Match Interrupt Enable
	128	// TICIE: Timer/Counter Input Capture Interrupt Enable
	129
	130	// interrupts_init...
	131	// General Interrupt Mask Register (enables interrupts)
	132	GIMSK \|= (1<<INT0);
	133	// GICR \|= (1<<INT0);
	134	// MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
	135	MCUCR \|= (1<<ISC01) \| (1<<ISC00); // any logical change generates interrupt
	136	INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
	137	/// loworhigh.bit = 0;
	138	}
	139	*/