Add 'software/' from commit 'e2b37ffacd2b3e76fd849fc046466568d5ac0779'

git-subtree-dir: software git-subtree-mainline: 255dcc3f40ed28aeb3da883c34547ffa781dc749 git-subtree-split: e2b37ffacd2b3e76fd849fc046466568d5ac0779
author: Max Christian Pohle 2017-06-05 16:24:20 +0200
committer: Max Christian Pohle 2017-06-05 16:24:20 +0200
commit: acf1faceeeb6461bb3c8c8266507151193f649b1 (patch)
tree: 89623374c3ba4a9288d82f51505374ac4ad24d25 /software/inc/int/dcf77.c
parent: 255dcc3f40ed28aeb3da883c34547ffa781dc749 (diff)
parent: e2b37ffacd2b3e76fd849fc046466568d5ac0779 (diff)
download: binwatch-mini-acf1faceeeb6461bb3c8c8266507151193f649b1.tar.bz2
binwatch-mini-acf1faceeeb6461bb3c8c8266507151193f649b1.zip
1 files changed, 123 insertions, 0 deletions
diff --git a/software/inc/int/dcf77.c b/software/inc/int/dcf77.c
new file mode 100755
index 0000000..31f1663
--- /dev/null
+++ b/software/inc/int/dcf77.c
@@ -0,0 +1,123 @@
+// vim:set et sw=2 ts=2 tw=120:
+#include "dcf77.h"
+// 7372800/a=10000
+// 115200 / a * x = 10000
+// 7372800/8/150
+// returns -1 on error
+unsigned char getBits(const DCF start, const char len)
+{
+  static const unsigned char mult[]  = {1, 2, 4, 8, 10, 20, 40, 80};
+  /// unsigned char p = 1; //parity
+  unsigned char r = 0; // retval
+  unsigned char i;
+  for(i=0; i<len; i++)
+    r += dcf77[start+i].bit * mult[i];
+    /// if(dcf77[start+i].bit)
+      /// p ^= 1;
+  return r;
+}
+// interrupt service routine (ISR) for timer 0 A compare match
+ISR(TIMER0_COMPB_vect)
+{
+}
+// ISR(TIMER0A_COMP_vect)
+ISR(TIMER0_COMPA_vect)
+{
+  interval++;
+  if (++t_current.ms >= 1000) // one second
+  {
+    t_current.ms = 0; // restart
+    if (++t_current.s > 59) // one minute
+    {
+      t_current.s = 0; // restart
+      if (++t_current.m > 59) // one hour
+      {
+        t_current.m = 0; // restart
+        if (++t_current.h > 23) // one day
+        {
+          t_current.h = 0; // restart
+          t_current.dd++;
+        }
+      }
+    }
+  }
+}
+ISR(INT0_vect)
+{
+}
+ISR(PCINT0_vect)
+{
+  // if(INT0_CONTROL == INT0_RISING_EDGE)
+  // if(MCUCR & (1<<ISC00))
+  // {
+  if (interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
+  {
+    if(dcf77_bit == 59) // check if every bit has been transfered
+    {
+      t_current.m  = getBits(DCF_MIN,     7);
+      t_current.h  = getBits(DCF_HOUR,    6);
+      t_current.dd = getBits(DCF_DAY,     6);
+      t_current.wd = getBits(DCF_WEEKDAY, 3);
+      t_current.mm = getBits(DCF_MONTH,   5);
+      t_current.yy = getBits(DCF_YEAR,    8);
+    }
+    // 59th second: synchronize with receiver...
+    dcf77_bit = 0;
+    t_current.s = 0;
+    t_current.ms = 0;
+    // falling edge causes interrupt...
+    // INT0_CONTROL = INT0_FALLING_EDGE;
+  }
+  else // INT0_FALLING_EDGE
+  {
+    if(interval > 50 && interval < 150)
+      dcf77[dcf77_bit++].bit = 0;
+    else if(interval > 150 && interval < 250)
+      dcf77[dcf77_bit++].bit = 1;
+    // rising edge causes interrupt...
+    // INT0_CONTROL = INT0_RISING_EDGE;
+  }
+  TCNT0 = 0;
+  interval = 0;
+}
+/*
+void timer_init()
+{
+  // 7372800/8
+  // >>>>>> DDRD &= ~((1<<PD2) | (1<<PD3)); // make INT0 and INT1 input-pins
+  // Prescaler...
+  // output compare...
+  //OCR0   = 152 - 1;
+  //TCCR0 |= (0<<WGM01) | (1<<WGM01);
+  // ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
+  // ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
+  // CSx: set prescaler (010 means 8)
+  /// TCCR1B = (1<<ICNC1) | (1<<ICES1) | (0<<CS12) | (1<<CS11) | (0<<CS10);
+  // OCIE0: Output Compare Match Interrupt Enable
+  // TICIE: Timer/Counter Input Capture Interrupt Enable
+  // interrupts_init...
+  // General Interrupt Mask Register (enables interrupts)
+  GIMSK |= (1<<INT0);
+  // GICR |= (1<<INT0);
+  // MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
+  MCUCR |= (1<<ISC01) | (1<<ISC00); // any logical change generates interrupt
+  INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
+  /// loworhigh.bit = 0;
+}
+*/
author	Max Christian Pohle	2017-06-05 16:24:20 +0200
committer	Max Christian Pohle	2017-06-05 16:24:20 +0200
commit	acf1faceeeb6461bb3c8c8266507151193f649b1 (patch)
tree	89623374c3ba4a9288d82f51505374ac4ad24d25 /software/inc/int/dcf77.c
parent	255dcc3f40ed28aeb3da883c34547ffa781dc749 (diff)
parent	e2b37ffacd2b3e76fd849fc046466568d5ac0779 (diff)
download	binwatch-mini-acf1faceeeb6461bb3c8c8266507151193f649b1.tar.bz2 binwatch-mini-acf1faceeeb6461bb3c8c8266507151193f649b1.zip

diff --git a/software/inc/int/dcf77.c b/software/inc/int/dcf77.c new file mode 100755 index 0000000..31f1663 --- /dev/null +++ b/software/inc/int/dcf77.c
@@ -0,0 +1,123 @@
	1	// vim:set et sw=2 ts=2 tw=120:
	2	#include "dcf77.h"
	3
	4	// 7372800/a=10000
	5	// 115200 / a * x = 10000
	6	// 7372800/8/150
	7
	8	// returns -1 on error
	9	unsigned char getBits(const DCF start, const char len)
	10	{
	11	static const unsigned char mult[] = {1, 2, 4, 8, 10, 20, 40, 80};
	12	/// unsigned char p = 1; //parity
	13	unsigned char r = 0; // retval
	14	unsigned char i;
	15	for(i=0; i<len; i++)
	16	r += dcf77[start+i].bit * mult[i];
	17	/// if(dcf77[start+i].bit)
	18	/// p ^= 1;
	19	return r;
	20	}
	21
	22	// interrupt service routine (ISR) for timer 0 A compare match
	23	ISR(TIMER0_COMPB_vect)
	24	{
	25
	26	}
	27
	28	// ISR(TIMER0A_COMP_vect)
	29	ISR(TIMER0_COMPA_vect)
	30	{
	31	interval++;
	32	if (++t_current.ms >= 1000) // one second
	33	{
	34	t_current.ms = 0; // restart
	35	if (++t_current.s > 59) // one minute
	36	{
	37	t_current.s = 0; // restart
	38	if (++t_current.m > 59) // one hour
	39	{
	40	t_current.m = 0; // restart
	41	if (++t_current.h > 23) // one day
	42	{
	43	t_current.h = 0; // restart
	44	t_current.dd++;
	45	}
	46	}
	47	}
	48	}
	49	}
	50
	51	ISR(INT0_vect)
	52	{
	53	}
	54
	55	ISR(PCINT0_vect)
	56	{
	57	// if(INT0_CONTROL == INT0_RISING_EDGE)
	58	// if(MCUCR & (1<<ISC00))
	59	// {
	60	if (interval > 1000 && interval < 2000) // 59th second - no rising edge at the beginning
	61	{
	62	if(dcf77_bit == 59) // check if every bit has been transfered
	63	{
	64	t_current.m = getBits(DCF_MIN, 7);
	65	t_current.h = getBits(DCF_HOUR, 6);
	66	t_current.dd = getBits(DCF_DAY, 6);
	67	t_current.wd = getBits(DCF_WEEKDAY, 3);
	68	t_current.mm = getBits(DCF_MONTH, 5);
	69	t_current.yy = getBits(DCF_YEAR, 8);
	70	}
	71
	72	// 59th second: synchronize with receiver...
	73	dcf77_bit = 0;
	74	t_current.s = 0;
	75	t_current.ms = 0;
	76
	77	// falling edge causes interrupt...
	78	// INT0_CONTROL = INT0_FALLING_EDGE;
	79	}
	80	else // INT0_FALLING_EDGE
	81	{
	82	if(interval > 50 && interval < 150)
	83	dcf77[dcf77_bit++].bit = 0;
	84	else if(interval > 150 && interval < 250)
	85	dcf77[dcf77_bit++].bit = 1;
	86
	87	// rising edge causes interrupt...
	88	// INT0_CONTROL = INT0_RISING_EDGE;
	89	}
	90
	91	TCNT0 = 0;
	92	interval = 0;
	93	}
	94
	95	/*
	96	void timer_init()
	97	{
	98	// 7372800/8
	99	// >>>>>> DDRD &= ~((1<<PD2) \| (1<<PD3)); // make INT0 and INT1 input-pins
	100
	101	// Prescaler...
	102	// output compare...
	103
	104	//OCR0 = 152 - 1;
	105	//TCCR0 \|= (0<<WGM01) \| (1<<WGM01);
	106
	107	// ICNC1 (Input Capture Noise Canceler (4 CKs) Timer/Counter 1
	108	// ICES1 (Input Capture Edge Select Timer/Counter 1) - 1:increasing 0:falling
	109	// CSx: set prescaler (010 means 8)
	110	/// TCCR1B = (1<<ICNC1) \| (1<<ICES1) \| (0<<CS12) \| (1<<CS11) \| (0<<CS10);
	111	// OCIE0: Output Compare Match Interrupt Enable
	112	// TICIE: Timer/Counter Input Capture Interrupt Enable
	113
	114	// interrupts_init...
	115	// General Interrupt Mask Register (enables interrupts)
	116	GIMSK \|= (1<<INT0);
	117	// GICR \|= (1<<INT0);
	118	// MCU Control Register (controls CPU-behaviours like interrupts & sleepmode)
	119	MCUCR \|= (1<<ISC01) \| (1<<ISC00); // any logical change generates interrupt
	120	INT0_CONTROL = INT0_RISING_EDGE; // going to toggle int0-behaviour
	121	/// loworhigh.bit = 0;
	122	}
	123	*/